UTS6710/drivers/hdmi/6710/hdmi_hw.c

#include <linux/kernel.h>  /* printk */
#include "sysreg.h"
#include "hdmi_hw.h"
#include "hdmi_dbg.h"
#include "drv_hdmi_internal.h"
#include "hdmi_hpd.h"
#include "hdmi_time.h"
#include "drv_hdmi_external.h"
#include "hdmi_infoframe_api.h"

#ifdef CONFIG_HDMI_SUPPORT_MHL
#include "cbus_drv.h"
#endif


#define HDMI_MMIO_BASE	  0xBE0E0000
#define HDMIPhy_MMIO_BASE   0xBE0E1000
#define CEC_MMIO_BASE	   0xBE1E0000
#define HDMI_CBUS_MMIO_BASE	   0xBE290000

#define HDMI_GetRegisterStartBit(ulRegisterName)	((ulRegisterName >> 16) & 0x00000003F)
#define HDMI_GetRegisterEndBit(ulRegisterName)	((ulRegisterName >> 22) & 0x00000003F)
#define GET_VALUE_BITS(ulRegisterName, ulValue) ((UINT32)(ulValue << (32 - HDMI_GetRegisterEndBit(ulRegisterName)))) >> ((32 - HDMI_GetRegisterEndBit(ulRegisterName)))
#define POSITION_VALUE(ulRegisterName, ulValue) (ulValue << HDMI_GetRegisterStartBit(ulRegisterName))
#define HDMI_GetStartAndEndBits(ulRegisterName)  (ulRegisterName & 0x0FFF0000)
#define ALL_BITS        0x08000000
#define WIDTH_BIT_8	    0x02000000
#define REGISTER_ADDRESS_MASK   0x0000FFFF
#define REGISTER_TYPE_MASK      0xF0000000

extern BOOL MHL_CABLE_IN;
extern BOOL MHL_CTS;
extern BOOL SWITCH_FIX_EQ;
HDMI_EQ_INDEX_e HDMI_EQ_MODE_INDEX=HDMI_EQ_INDEX_DEFAULT;

UINT32 HDMI_GetRegisterType(UINT32 ulRegisterType)
{
    switch (ulRegisterType)
    {
        case 0x40000000:	//HDMIRX
            return HDMI_MMIO_BASE;
        case 0x50000000:	//CEC
            return CEC_MMIO_BASE;
        case 0x60000000:	//HDMIRX CBUS
            return HDMI_CBUS_MMIO_BASE;
        default:
            return HDMI_MMIO_BASE;
    }
}


//****************************************************************************
//
// Function   : HDMI_RegisterWrite
// Params    : ulRegisterName -address of the index register
//                  ulValue - value to program to the given bits of the register
// Description: Sets the given bits of the given index register to the given value
// ulRegisterName data format:  TTTT WWWW WWSS SSSS AAAA AAAA AAAA AAAA
//		                                   0:reserved
//							T:register type  4=HDMIRX_register (offset 0xBE0E)
//							W:register used width
//							S:register start bit
//							A:register address
// Returns    : void
//****************************************************************************
void HDMI_RegisterWrite(UINT32 ulRegisterName, UINT32 ulValue)
{
	UINT32 ulData, ulBitMask, ulRegisterType, ulRegisterAddr;
	BOOL fUseByteAccess;
	volatile UINT32 *pdRegAddr32;
	volatile UINT8 *pbRegAddr8;
	
	ulRegisterType = HDMI_GetRegisterType(ulRegisterName & REGISTER_TYPE_MASK);
	ulBitMask = GET_VALUE_BITS(ulRegisterName, 0xFFFFFFFF);
	ulBitMask <<= HDMI_GetRegisterStartBit(ulRegisterName);
	ulValue <<= HDMI_GetRegisterStartBit(ulRegisterName);

	fUseByteAccess = (HDMI_GetStartAndEndBits(ulRegisterName) <= WIDTH_BIT_8)?TRUE:FALSE;

	ulRegisterAddr =  (ulRegisterName & REGISTER_ADDRESS_MASK);
	ulRegisterAddr |= ulRegisterType;		//offset address

	pdRegAddr32 = (UINT32 *)ulRegisterAddr;
	pbRegAddr8 = (UINT8 *)ulRegisterAddr;

	if(fUseByteAccess)
	{
		ulData = *pbRegAddr8;
	}
	else
	{
		ulData = *pdRegAddr32;
	}

	ulData &= ~ulBitMask;
	ulData |= (ulValue & ulBitMask);

	if(fUseByteAccess)
	{
		*pbRegAddr8 = ulData;
	}
	else
	{
		*pdRegAddr32 = ulData;
	}

}

//****************************************************************************
//
// Function   : HDMI_RegisterRead
// Params    : ulRegisterName -address of the index register
// Description: read the given bits of the given index register to the value
// ulRegisterName data format:  TTTT WWWW WWSS SSSS AAAA AAAA AAAA AAAA
//		                                   0:reserved
//							T:register type  4=HDMIRX_register (offset 0xBE0E)
//							W:register used width
//							S:register start bit
//							A:register address
// Returns    : register data
//****************************************************************************
UINT32 HDMI_RegisterRead(UINT32 ulRegisterName)
{
	UINT32 ulData, ulBitMask, ulRegisterType, ulRegisterNameTmp;
	volatile UINT32 *pdRegAddr32;
	
	ulRegisterNameTmp = ulRegisterName;
	ulRegisterType = HDMI_GetRegisterType(ulRegisterName & REGISTER_TYPE_MASK);
	ulRegisterNameTmp &= REGISTER_ADDRESS_MASK;
	ulRegisterNameTmp |= ulRegisterType; //offset address

	pdRegAddr32 = (UINT32 *)ulRegisterNameTmp;
	
	ulData = *pdRegAddr32;

	if (HDMI_GetStartAndEndBits(ulRegisterName) != ALL_BITS)
	{
		ulBitMask = GET_VALUE_BITS(ulRegisterName, 0xFFFFFFFF);
		ulBitMask <<= HDMI_GetRegisterStartBit(ulRegisterName);
		ulData &= ulBitMask;
		ulData >>=  (HDMI_GetRegisterStartBit(ulRegisterName));
	}
	
	return ulData;
}



void HDMI_Interrupt_Enable(UINT32 ulIntr)
{
	UINT32 ulCurIntEn;
	ulCurIntEn = HDMI_RegisterRead(HDMIRX_R_INTR_en);
	ulCurIntEn |= ulIntr;
	HDMI_RegisterWrite(HDMIRX_R_INTR_en, ulCurIntEn);
}

void HDMI_Interrupt_Disable(UINT32 ulIntr)
{
	UINT32 ulCurIntEn;
	ulCurIntEn = HDMI_RegisterRead(HDMIRX_R_INTR_en);
	ulCurIntEn &= ~(ulIntr);
	HDMI_RegisterWrite(HDMIRX_R_INTR_en, ulCurIntEn);
}


void HDMI_PHY_Enable(BOOL fEn)
{
	if(fEn)
	{
		HDMI_Set_PLL_Mode(HDMI_PLL_MODE_HDMI_ENABLE);
		#ifdef CONFIG_HDMI_SUPPORT_MHL
		if((MHL_CABLE_IN == TRUE)&&( DrvHDMIPortSelectBitsGet()==CONFIG_HDMI_MHL_PORT))
			HDMI_MHL_RxSense_Term_Debug(FALSE);	//auto HDMI or MHL mode
		else
			HDMI_MHL_RxSense_Term_Debug(TRUE);	//force HDMI mode for debug(not MHL mode)
		#else
		HDMI_MHL_RxSense_Term_Debug(TRUE);	//force HDMI mode for debug(not MHL mode)
		#endif
	}
	else		//Power Down for CEC	
	{
		HDMI_Set_PLL_Mode(HDMI_PLL_MODE_HDMI_DISABLE);
	}
#ifdef USE_HW_ADAPTIVE_EQ
#ifdef CONFIG_HDMI_SUPPORT_MHL
    if((MHL_CABLE_IN != TRUE)||( DrvHDMIPortSelectBitsGet() != CONFIG_HDMI_MHL_PORT))
#endif
    {
	    HDMI_Adaptive_EQ_Init();
    }
#endif
}


void HDMI_PLL_Init(void)
{
	HDMI_Set_PLL_Mode(HDMI_PLL_MODE_HDMI_INIT);
}


void HDMI_SetPLL_ByFreq(void)
{
	UINT8 bRefFreq = HDMI_RegisterRead(HDMIRX_ref_freq_cnt);
	HDMI_RegisterWrite(HDMIRX_TMDSCLK_PP_SEL, 0);
	
	if(bRefFreq <= 0x6)
	{
		hdmidbg("bRefFreq ?~0x6\n");
		HDMI_Set_PLL_Mode(HDMI_PLL_MODE_HDMI_FREQ_6);
	}
	else if(bRefFreq >= 0x7 && bRefFreq <= 0xF)
	{
		hdmidbg("bRefFreq 0x7~0xF\n");
		HDMI_Set_PLL_Mode(HDMI_PLL_MODE_HDMI_FREQ_7_F);
	}
	else if(bRefFreq >= 0x10 && bRefFreq <= 0x1E)
	{
		hdmidbg("bRefFreq 0x10~0x1E\n");
		HDMI_Set_PLL_Mode(HDMI_PLL_MODE_HDMI_FREQ_10_1E);
	}
	else if(bRefFreq >= 0x1F && bRefFreq <= 0x32)
	{
		hdmidbg("bRefFreq 0x1F~0x32\n");
		HDMI_Set_PLL_Mode(HDMI_PLL_MODE_HDMI_FREQ_1F_32);
	}
	else if(bRefFreq >= 0x33 && bRefFreq <= 0x3D)
	{
		hdmidbg("bRefFreq 0x33~0x3D\n");
		HDMI_Set_PLL_Mode(HDMI_PLL_MODE_HDMI_FREQ_33_3D);
	}
	else if(bRefFreq >= 0x3E && bRefFreq <= 0x60)
	{
		hdmidbg("bRefFreq 0x3E~0x60\n");
		HDMI_Set_PLL_Mode(HDMI_PLL_MODE_HDMI_FREQ_3E_60);
	}
	else if(bRefFreq >= 0x61)
	{
		hdmidbg("bRefFreq 0x61~?\n");
		HDMI_Set_PLL_Mode(HDMI_PLL_MODE_HDMI_FREQ_61);
	}
	hdmidbg("bPLL_ICtrl=0x%x\n", HDMI_RegisterRead(HDMIRX_PLL_ICTRL_3_0_));
	hdmidbg("EN_FDIV=0x%x\n", HDMI_RegisterRead(HDMIRX_PLL_EN_FDIV));
	hdmidbg("bPLL_GB=0x%x\n", HDMI_RegisterRead(HDMIRX_PLL_GB_3_0_) );
	hdmidbg("DIVSLE2=0x%x\n", HDMI_RegisterRead(HDMIRX_PHY_DIVSLE2));
	hdmidbg("DIV_SEL_2=0x%x\n", HDMI_RegisterRead(HDMIRX_PLL_DIVSEL2));	
	hdmidbg("REFDIV=0x%x\n", HDMI_RegisterRead(HDMIRX_PLL_REFDIV));
	
}

void HDMI_MHL_SetPLL_ByFreq(void)
{
	UINT8 bRefFreq = HDMI_RegisterRead(HDMIRX_ref_freq_cnt);
#ifdef USE_HW_ADAPTIVE_EQ
#ifndef Manu_EQ_Adjust
    UINT8 bHDMIRX_BS3 = (UINT8)HDMI_RegisterRead(HDMIRX_BS3);
#endif
#endif
	HDMI_RegisterWrite(HDMIRX_R_BYTE_ALIGN_CNT2, 0xF);//For Silicon Image MHL Starter KIT-9244 
	
	if((HDMI_RegisterRead(HDMIRX_cbus_mode_pathen_muted)&0x3) ==0x2)
	{//CLK_MODE=10 =>PP Mode
		hdmidbg("MHL PP Mode\n");
#ifndef Manu_EQ_Adjust
		HDMI_RegisterWrite(CTRLI_631_600__DW_0430,0x33722033);
		HDMI_RegisterWrite(CTRLI_663_632__DW_0434,0x20337220);
#ifdef USE_HW_ADAPTIVE_EQ
		//HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00000072);
#ifdef CONFIG_HDMI_SUPPORT_MHL
        if((MHL_CABLE_IN == TRUE)&&( DrvHDMIPortSelectBitsGet() == CONFIG_HDMI_MHL_PORT))
        {
            HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00000072);
        }
        else
#endif
        {
    		HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00000072|(bHDMIRX_BS3<<16));
        }
#else
		HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00000072);
#endif
#endif
		HDMI_RegisterWrite(HDMIRX_R_SP1_EQ_OUT_VREF0,0);
		HDMI_RegisterWrite(HDMIRX_R_SP1_EQ_OUT_VREF1,1);
		HDMI_RegisterWrite(HDMIRX_BIAS_VREF_SF_SEL_1_0_, 3);
		HDMI_RegisterWrite(HDMIRX_EQ_VDC_SEL, 0);

		HDMI_RegisterWrite(HDMIRX_EQ_ICTL0, 0x1);
		HDMI_RegisterWrite(HDMIRX_EQ_ICTL1, 0x1);
		HDMI_RegisterWrite(HDMIRX_PHY_IB_CT_CK, 0x0);

        HDMI_RegisterWrite(HDMIRX_ALN_SEL, 0);
        HDMI_RegisterWrite(HDMIRX_de_lo, 0);    //Disable hw adaptive eq condition more stricter

		HDMI_RegisterWrite(HDMIRX_TMDSCLK_PP_SEL, 1);
		//*((u8  *)0xbe0e001c) =  0xff;
		HDMI_RegisterWrite(HDMIRX_HDMIP0_Mode_Sel_external, 1);
		HDMI_RegisterWrite(HDMIRX_HDMIP0_Mode_Sel_mux, 1);
		HDMI_RegisterWrite(HDMIRX_HDMIP0_MHL_Mode_Sel_external, 1);
		HDMI_RegisterWrite(HDMIRX_HDMIP0_MHL_Mode_Sel_mux, 1);
		HDMI_RegisterWrite(HDMIRX_HDMIP0_Mode_Sel_PLL_external, 1);
		HDMI_RegisterWrite(HDMIRX_HDMIP0_Mode_Sel_PLL_mux, 1);
		HDMI_RegisterWrite(HDMIRX_HDMIP0_MHL_Mode_PLL_Sel_external, 1);
		HDMI_RegisterWrite(HDMIRX_HDMIP0_MHL_Mode_Sel_PLL_mux, 1);

		if(bRefFreq <= 0xA)
		{
		    //TMDS Clk < 26Mhz
			hdmidbg("bRefFreq ?~0xA\n");
			HDMI_RegisterWrite(HDMIRX_PLL_ICTRL_3_0_, 0x5);
			HDMI_RegisterWrite(HDMIRX_PLL_EN_FDIV, 0);
			HDMI_RegisterWrite(HDMIRX_PLL_GB_3_0_, 0x4);
			HDMI_RegisterWrite(HDMIRX_PLL_GB_5_4, 1);//LPF CAP sel
			HDMI_RegisterWrite(HDMIRX_PLL_FEBDIV_7_0_, 19);
            HDMI_RegisterWrite(HDMIRX_R_SP6, 0);
            HDMI_RegisterWrite(HDMIRX_R_SP7, 0);
            HDMI_RegisterWrite(HDMIRX_R_SP9, 1);
			//HDMI_RegisterWrite(HDMIRX_CTL_R_MORECTRLI_15_0_, 0x0039);
			HDMI_RegisterWrite(HDMIRX_CTL_R_MORECTRLI_15_0_, 0x0031);
            HDMI_RegisterWrite(HDMIRX_CTL_R_LOCK_CNT_3_0_, 0xf);
		}
		else if(bRefFreq >= 0xB && bRefFreq <= 0x10)
		{
		    //28.6Mhz <TMDS Clk < 41.6Mhz
			hdmidbg("bRefFreq 0xB~0x10\n");
			HDMI_RegisterWrite(HDMIRX_PLL_ICTRL_3_0_, 0x5);
			HDMI_RegisterWrite(HDMIRX_PLL_EN_FDIV, 0);
			HDMI_RegisterWrite(HDMIRX_PLL_GB_3_0_, 0xa);
			HDMI_RegisterWrite(HDMIRX_PLL_GB_5_4, 1);//LPF CAP sel
			HDMI_RegisterWrite(HDMIRX_PLL_FEBDIV_7_0_, 19);
            HDMI_RegisterWrite(HDMIRX_R_SP6, 0);
            HDMI_RegisterWrite(HDMIRX_R_SP7, 0);
            HDMI_RegisterWrite(HDMIRX_R_SP9, 1);
			//HDMI_RegisterWrite(HDMIRX_CTL_R_MORECTRLI_15_0_, 0x0039);
			HDMI_RegisterWrite(HDMIRX_CTL_R_MORECTRLI_15_0_, 0x0031);
            HDMI_RegisterWrite(HDMIRX_CTL_R_LOCK_CNT_3_0_, 0xf);
		}
		else if(bRefFreq >= 0x11 && bRefFreq <= 0x15)
		{
		    //44.2Mhz <TMDS Clk < 54.6Mhz
			hdmidbg("bRefFreq 0x11~0x15\n");
			HDMI_RegisterWrite(HDMIRX_PLL_ICTRL_3_0_, 0x5);
			HDMI_RegisterWrite(HDMIRX_PLL_EN_FDIV, 0);
			HDMI_RegisterWrite(HDMIRX_PLL_GB_3_0_, 0x4);
			HDMI_RegisterWrite(HDMIRX_PLL_GB_5_4, 0);//LPF CAP sel
			HDMI_RegisterWrite(HDMIRX_PLL_FEBDIV_7_0_, 9);
            HDMI_RegisterWrite(HDMIRX_R_SP6, 0);
            HDMI_RegisterWrite(HDMIRX_R_SP7, 0);
            HDMI_RegisterWrite(HDMIRX_R_SP9, 1);
			//HDMI_RegisterWrite(HDMIRX_CTL_R_MORECTRLI_15_0_, 0x0038);
			HDMI_RegisterWrite(HDMIRX_CTL_R_MORECTRLI_15_0_, 0x0030);
            HDMI_RegisterWrite(HDMIRX_CTL_R_LOCK_CNT_3_0_, 0xf);
		}
		else if(bRefFreq >= 0x16)
		{
		    //57.2Mhz <TMDS Clk
			hdmidbg("bRefFreq 0x16~?\n");
			HDMI_RegisterWrite(HDMIRX_PLL_ICTRL_3_0_, 0x5);// 2->3
			HDMI_RegisterWrite(HDMIRX_PLL_EN_FDIV, 0);
			HDMI_RegisterWrite(HDMIRX_PLL_GB_3_0_, 0x9);
			HDMI_RegisterWrite(HDMIRX_PLL_GB_5_4, 0);//LPF CAP sel
			HDMI_RegisterWrite(HDMIRX_PLL_FEBDIV_7_0_, 9);
            HDMI_RegisterWrite(HDMIRX_R_SP6, 0);
            HDMI_RegisterWrite(HDMIRX_R_SP7, 0);
            HDMI_RegisterWrite(HDMIRX_R_SP9, 1);
			//HDMI_RegisterWrite(HDMIRX_CTL_R_MORECTRLI_15_0_, 0x0038);
			HDMI_RegisterWrite(HDMIRX_CTL_R_MORECTRLI_15_0_, 0x0030);
            HDMI_RegisterWrite(HDMIRX_CTL_R_LOCK_CNT_3_0_, 0xf);
		}

		HDMI_RegisterWrite(HDMIRX_CTL_R_FG_CNT_7_0_, 0x5);
		HDMI_RegisterWrite(HDMIRX_CTL_R_FH_CNT_7_0_, 0x7);
		HDMI_RegisterWrite(HDMIRX_CTL_R_FI_CNT_7_0_, 0x9);
		HDMI_RegisterWrite(HDMIRX_CTL_R_FJ_CNT_7_0_, 0xB);
		HDMI_RegisterWrite(HDMIRX_CTL_R_FK_CNT_7_0_, 0x15);
		HDMI_RegisterWrite(HDMIRX_PHY_DIVSLE2, 0);
		HDMI_RegisterWrite(HDMIRX_PLL_DIVSEL2, 0);
		HDMI_RegisterWrite(HDMIRX_PLL_REFDIV, 0);
	
	}
	else
	{//CLK_MODE=11 =>24 Bit Mode
		hdmidbg("MHL 24 Bit Mode\n");
		HDMI_RegisterWrite(HDMIRX_TMDSCLK_PP_SEL, 0);
#ifndef Manu_EQ_Adjust
		HDMI_RegisterWrite(CTRLI_631_600__DW_0430,0x04771004);
		HDMI_RegisterWrite(CTRLI_663_632__DW_0434,0x10047710);
#ifdef USE_HW_ADAPTIVE_EQ
		//HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00000072);
#ifdef CONFIG_HDMI_SUPPORT_MHL
       if((MHL_CABLE_IN == TRUE)&&( DrvHDMIPortSelectBitsGet() == CONFIG_HDMI_MHL_PORT))
        {
            HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00000077);
        }
        else
#endif
        {
            HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00000077|(bHDMIRX_BS3<<16));
        }
#else
		HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00000077);
#endif
#endif
		HDMI_RegisterWrite(HDMIRX_R_SP1_EQ_OUT_VREF0,0);
		HDMI_RegisterWrite(HDMIRX_R_SP1_EQ_OUT_VREF1,1);
		HDMI_RegisterWrite(HDMIRX_BIAS_VREF_SF_SEL_1_0_, 1);
		HDMI_RegisterWrite(HDMIRX_EQ_VDC_SEL, 1);

		HDMI_RegisterWrite(HDMIRX_EQ_ICTL0, 0x0);
		HDMI_RegisterWrite(HDMIRX_EQ_ICTL1, 0x1);
		HDMI_RegisterWrite(HDMIRX_PHY_IB_CT_CK, 0x2);

		//*((u8  *)0xbe0e001c) =  0xbb;
		HDMI_RegisterWrite(HDMIRX_HDMIP0_Mode_Sel_external, 1);
		HDMI_RegisterWrite(HDMIRX_HDMIP0_Mode_Sel_mux, 1);
		HDMI_RegisterWrite(HDMIRX_HDMIP0_MHL_Mode_Sel_external, 0);
		HDMI_RegisterWrite(HDMIRX_HDMIP0_MHL_Mode_Sel_mux, 1);
		HDMI_RegisterWrite(HDMIRX_HDMIP0_Mode_Sel_PLL_external, 1);
		HDMI_RegisterWrite(HDMIRX_HDMIP0_Mode_Sel_PLL_mux, 1);
		HDMI_RegisterWrite(HDMIRX_HDMIP0_MHL_Mode_PLL_Sel_external, 0);
		HDMI_RegisterWrite(HDMIRX_HDMIP0_MHL_Mode_Sel_PLL_mux, 1);
	
		if(bRefFreq <= 0xA)
		{
		    //TMDS Clk < 26Mhz
			hdmidbg("bRefFreq ?~0xA\n");
			HDMI_RegisterWrite(HDMIRX_PLL_ICTRL_3_0_, 0x5);//6->9
			HDMI_RegisterWrite(HDMIRX_PLL_EN_FDIV, 0);
			HDMI_RegisterWrite(HDMIRX_PLL_GB_3_0_, 0xa);
			HDMI_RegisterWrite(HDMIRX_PLL_GB_5_4, 3);//LPF CAP sel
			HDMI_RegisterWrite(HDMIRX_PLL_FEBDIV_7_0_, 59);
            HDMI_RegisterWrite(HDMIRX_R_SP6, 0);
            HDMI_RegisterWrite(HDMIRX_R_SP7, 0);
            HDMI_RegisterWrite(HDMIRX_R_SP9, 0);
			//HDMI_RegisterWrite(HDMIRX_CTL_R_MORECTRLI_15_0_, 0x003a);
			HDMI_RegisterWrite(HDMIRX_CTL_R_MORECTRLI_15_0_, 0x0032);
            HDMI_RegisterWrite(HDMIRX_CTL_R_LOCK_CNT_3_0_, 0xf);
		}
		else if(bRefFreq >= 0xB && bRefFreq <= 0x10)
		{
		    //28.6Mhz <TMDS Clk < 41.6Mhz
			hdmidbg("bRefFreq 0xB~0x10\n");
			HDMI_RegisterWrite(HDMIRX_PLL_ICTRL_3_0_, 0x5);// 4->3
			HDMI_RegisterWrite(HDMIRX_PLL_EN_FDIV, 0);
			HDMI_RegisterWrite(HDMIRX_PLL_GB_3_0_, 0x5);// 8D->6
			HDMI_RegisterWrite(HDMIRX_PLL_GB_5_4, 1);//LPF CAP sel
			HDMI_RegisterWrite(HDMIRX_PLL_FEBDIV_7_0_, 29);
            HDMI_RegisterWrite(HDMIRX_R_SP6, 0);
            HDMI_RegisterWrite(HDMIRX_R_SP7, 0);
            HDMI_RegisterWrite(HDMIRX_R_SP9, 0);
			//HDMI_RegisterWrite(HDMIRX_CTL_R_MORECTRLI_15_0_, 0x0039);
			HDMI_RegisterWrite(HDMIRX_CTL_R_MORECTRLI_15_0_, 0x0031);
            HDMI_RegisterWrite(HDMIRX_CTL_R_LOCK_CNT_3_0_, 0xf);
		}
		else if(bRefFreq >= 0x11 && bRefFreq <= 0x15)
		{
		    //44.2Mhz <TMDS Clk < 54.6Mhz
			hdmidbg("bRefFreq 0x11~0x15\n");
			HDMI_RegisterWrite(HDMIRX_PLL_ICTRL_3_0_, 0x5);
			HDMI_RegisterWrite(HDMIRX_PLL_EN_FDIV, 0);
			HDMI_RegisterWrite(HDMIRX_PLL_GB_3_0_, 0xc);
			HDMI_RegisterWrite(HDMIRX_PLL_GB_5_4, 1);//LPF CAP sel
			HDMI_RegisterWrite(HDMIRX_PLL_FEBDIV_7_0_, 29);
            HDMI_RegisterWrite(HDMIRX_R_SP6, 0);
            HDMI_RegisterWrite(HDMIRX_R_SP7, 0);
            HDMI_RegisterWrite(HDMIRX_R_SP9, 0);
			//HDMI_RegisterWrite(HDMIRX_CTL_R_MORECTRLI_15_0_, 0x0039);
			HDMI_RegisterWrite(HDMIRX_CTL_R_MORECTRLI_15_0_, 0x0031);
            HDMI_RegisterWrite(HDMIRX_CTL_R_LOCK_CNT_3_0_, 0xf);
		}
		else if(bRefFreq >= 0x16)
		{
		    //57.2Mhz <TMDS Clk
			hdmidbg("bRefFreq 0x16~?\n");
			HDMI_RegisterWrite(HDMIRX_PLL_ICTRL_3_0_, 0x5);// 2 ->3
			HDMI_RegisterWrite(HDMIRX_PLL_EN_FDIV, 0);
			HDMI_RegisterWrite(HDMIRX_PLL_GB_3_0_, 0x5);
			HDMI_RegisterWrite(HDMIRX_PLL_GB_5_4, 0);//LPF CAP sel
			HDMI_RegisterWrite(HDMIRX_PLL_FEBDIV_7_0_, 14);
            HDMI_RegisterWrite(HDMIRX_R_SP6, 0);
            HDMI_RegisterWrite(HDMIRX_R_SP7, 0);
            HDMI_RegisterWrite(HDMIRX_R_SP9, 0);
			//HDMI_RegisterWrite(HDMIRX_CTL_R_MORECTRLI_15_0_, 0x0038);
			HDMI_RegisterWrite(HDMIRX_CTL_R_MORECTRLI_15_0_, 0x0030);
            HDMI_RegisterWrite(HDMIRX_CTL_R_LOCK_CNT_3_0_, 0xf);
		}
		HDMI_RegisterWrite(HDMIRX_CTL_R_FG_CNT_7_0_, 0x5);
		HDMI_RegisterWrite(HDMIRX_CTL_R_FH_CNT_7_0_, 0x7);
		HDMI_RegisterWrite(HDMIRX_CTL_R_FI_CNT_7_0_, 0x9);
		HDMI_RegisterWrite(HDMIRX_CTL_R_FJ_CNT_7_0_, 0xB);
		HDMI_RegisterWrite(HDMIRX_CTL_R_FK_CNT_7_0_, 0x15);
		HDMI_RegisterWrite(HDMIRX_PHY_DIVSLE2, 0);
		HDMI_RegisterWrite(HDMIRX_PLL_DIVSEL2, 0);
		HDMI_RegisterWrite(HDMIRX_PLL_REFDIV, 0);
	}

}

void HDMI_MHL_CABLE_IN(BOOL fIn)
{
	if(fIn)	
	{
		MHL_CABLE_IN = TRUE;
	}
	else
	{
		MHL_CABLE_IN = FALSE;
	}
}

void HDMI_MHL_CTS(BOOL fIn)
{
	if(fIn)	
	{
		MHL_CTS = TRUE;
		sysset_HDMI_MHL_CBUS_EN_CTS_CTL(TRUE);
	}
	else
	{
		MHL_CTS = FALSE;
		sysset_HDMI_MHL_CBUS_EN_CTS_CTL(FALSE);
	}
}

void HDMI_Reset_HDMI_PLL(void)
{
#ifdef CONFIG_HDMI_SUPPORT_MHL
		if((MHL_CABLE_IN == TRUE)&&( DrvHDMIPortSelectBitsGet() == CONFIG_HDMI_MHL_PORT))
		{
			HDMI_RegisterWrite(HDMIRX_CTL_R_MORECTRLI_15_0_, 0x0020);
			HDMI_DelayMs(2);
			HDMI_RegisterWrite(HDMIRX_CTL_R_MORECTRLI_15_0_, 0x0038);
		}
		else
		{
            HDMI_RegisterWrite(HDMIRX_CTL_R_RSTJ, 0);
			HDMI_DelayMs(2);
			HDMI_RegisterWrite(HDMIRX_CTL_R_RSTJ, 1);
		}
#else
            HDMI_RegisterWrite(HDMIRX_CTL_R_RSTJ, 0);
			HDMI_DelayMs(2);
			HDMI_RegisterWrite(HDMIRX_CTL_R_RSTJ, 1);
#endif			
}

//set force to HDMI mode, (set 1: force HDMI mode)
void HDMI_MHL_RxSense_Term_Debug(BOOL fEn)
{
	if(fEn)	//force HDMI mode
	{
		HDMI_RegisterWrite(HDMIRX_R_RTT_INI_5_0_, 0x29);
		HDMI_RegisterWrite(HDMIRX_HDMIP0_Rx_Sense_external, 1);
		HDMI_RegisterWrite(HDMIRX_HDMIP0_Rx_Sense_mux, 1);
		HDMI_RegisterWrite(HDMIRX_HDMIP1_Rx_Sense_external, 1);
		HDMI_RegisterWrite(HDMIRX_HDMIP1_Rx_Sense_mux, 1);
		HDMI_RegisterWrite(HDMIRX_HDMIP2_Rx_Sense_external, 1);
		HDMI_RegisterWrite(HDMIRX_HDMIP2_Rx_Sense_mux, 1);	
		HDMI_RegisterWrite(CTRLI_303_272__DW_001C,0xBF2F3FEE);
		
	}
	else		//auto HDMI or MHL mode
	{
		HDMI_RegisterWrite(HDMIRX_R_RTT_INI_5_0_, 0x29);
		HDMI_RegisterWrite(HDMIRX_HDMIP0_Rx_Sense_external, 0);
		HDMI_RegisterWrite(HDMIRX_HDMIP0_Rx_Sense_mux, 0);
		HDMI_RegisterWrite(HDMIRX_HDMIP1_Rx_Sense_external, 0);
		HDMI_RegisterWrite(HDMIRX_HDMIP1_Rx_Sense_mux, 0);
		HDMI_RegisterWrite(HDMIRX_HDMIP2_Rx_Sense_external, 0);
		HDMI_RegisterWrite(HDMIRX_HDMIP2_Rx_Sense_mux, 0);	
		//HDMI_RegisterWrite(CTRLI_303_272__DW_001C,0x00000000);
		HDMI_RegisterWrite(CTRLI_303_272__DW_001C,0x80080F00);  //Enable P0,P1_Rx_Sense_internal & P0,P1_Rx_Sense_mux and adjust RTT_CM's setting
	}
}




extern UINT32 MAX_BCH_ERROR_CNT;
//set HDMI PLL for HDMI/DEMOD
void HDMI_Set_PLL_Mode(HDMI_PLL_MODE_e eHDMI_PLL_MODE)
{
	UINT8 bTerm = (UINT8)HDMI_RegisterRead(HDMIRX_PHY_RTT_EN_P_2_0_);
	UINT8 bPortSel = (UINT8)HDMI_RegisterRead(HDMIRX_PORT_EN_P2_0);
#ifdef USE_HW_ADAPTIVE_EQ
	UINT8 bEQ_FIX = (UINT8)HDMI_RegisterRead(HDMIRX_EQ_VAL_FIX);
	UINT8 bHDMIRX_BS2_0 = (UINT8)HDMI_RegisterRead(HDMIRX_bs_2_0_);
#ifndef Manu_EQ_Adjust	
	UINT8 bHDMIRX_BS3 = (UINT8)HDMI_RegisterRead(HDMIRX_BS3);
#endif
#endif

	hdmidbg("[H] %s mode:%d\n", __FUNCTION__, eHDMI_PLL_MODE);

	switch(eHDMI_PLL_MODE)
	{
		/* Common */
		case HDMI_PLL_MODE_INIT:
			//todo
			#if 1 //Set PLL DIV SEL default value to avoid video water wave interfere, junjie.hung suggest in 20140625
			HDMI_RegisterWrite(HDMIRX_PLL_FEBDIV_7_0_, 0x2f);
			#endif
			break;
		case HDMI_PLL_MODE_ON:
			//todo
			break;
		case HDMI_PLL_MODE_OFF:
			//todo
			HDMI_RegisterWrite(CTRLI_31_0__DW_0280   , 0x00080000);
			HDMI_RegisterWrite(CTRLI_47_32__DW_0284,0x000008C0);
			HDMI_RegisterWrite(CTRLI_79_48__DW_0000,0x00000088);
			break;
		/* HDMI */
		case HDMI_PLL_MODE_HDMI_INIT:
            HDMI_RegisterWrite(HDMIRX_PLL_PWDN_DEMOD, 0x1);
			HDMI_RegisterWrite(HDMIRX_PLL_RSTN, 1);
			HDMI_RegisterWrite(HDMIRX_R_SP5_PLL_CTP_PWDJ, 0x1);
			HDMI_RegisterWrite(HDMIRX_LDO_PWDE, 0x1);// 1/0 : normal / PD (change define from 331)
			HDMI_RegisterWrite(HDMIRX_LDO_PWD, 0x1);// 1/0 : normal / PD (change define from 331)
			
			//HDMI_RegisterWrite(HDMIRX_BIAS_VREF_SF_SEL_1_0_, 3);
			HDMI_RegisterWrite(HDMIRX_BIAS_VREF_SF_SEL_1_0_, 1);
			
			HDMI_RegisterWrite(HDMIRX_REG_CPS_CNT_TH0, 0);
			//HDMI_RegisterWrite(HDMIRX_debug_port_ext_31_28_, 0);
			HDMI_RegisterWrite(HDMIRX_reg_dport_ext, 0);
			
			HDMI_RegisterWrite(HDMIRX_PLL_EN_COMP, 1);
			//HDMI_RegisterWrite(HDMIRX_DEMOD_EN, 1);
			//HDMI_RegisterWrite(HDMIRX_PLL_RESETJ, 1);
			HDMI_RegisterWrite(HDMIRX_PLL_RESETJ, 0);
			HDMI_RegisterWrite(HDMIRX_r_zsink_cal_en, 0);
			HDMI_RegisterWrite(HDMIRX_REG_CPS_CNT_CLEAR, 0);
			HDMI_RegisterWrite(HDMIRX_w_con_1_0_, 0x0);
			HDMI_RegisterWrite(HDMIRX_w_con_3_2_, 0x3);
			HDMI_RegisterWrite(HDMIRX_w_con5_4, 0x1);
			break;
		case HDMI_PLL_MODE_HDMI_ENABLE:
			sysset_DEMOD_BG_POWER_DOWN(FALSE);
#ifdef USE_HW_ADAPTIVE_EQ
#ifdef CONFIG_HDMI_SUPPORT_MHL
            if((MHL_CABLE_IN == TRUE)&&( DrvHDMIPortSelectBitsGet() == CONFIG_HDMI_MHL_PORT))
            {
			    HDMI_RegisterWrite(CTRLI_31_0__DW_0280, 0x997F13A0);
            }
            else
#endif
            {
                HDMI_RegisterWrite(CTRLI_31_0__DW_0280, 0x997713A0| (bEQ_FIX<<19));//HDMIRX_EQ_VAL_FIX =0
            }
#else
			HDMI_RegisterWrite(CTRLI_31_0__DW_0280, 0x997F13A0);
#endif
			//HDMI_RegisterWrite(CTRLI_47_32__DW_0284,0xD5C6);
			HDMI_RegisterWrite(CTRLI_47_32__DW_0284,0xD8F9);
            #ifdef HDMI_USE_EXT_DIVSEL
			HDMI_RegisterWrite(CTRLI_79_48__DW_0000,0xAF00B880 | (bTerm<<4) | bPortSel); // force PLLRSTJ=1, PLLRSTJ=0, no refclk clock
			#else
            HDMI_RegisterWrite(CTRLI_79_48__DW_0000,0xAF00A880 | (bTerm<<4) | bPortSel); // force PLLRSTJ=1, PLLRSTJ=0, no refclk clock
            #endif
			HDMI_RegisterWrite(CTRLI_111_80__DW_0004,0x00000001);
			HDMI_RegisterWrite(CTRLI_143_112__DW_0008,0x0F010000);
			HDMI_RegisterWrite(CTRLI_175_144__DW_000C,0x1E100F0F);//533 18->1E
			HDMI_RegisterWrite(CTRLI_207_176__DW_0010,0x403F001F);//533 1C->1F
			HDMI_RegisterWrite(CTRLI_239_208__DW_0014,0x0);
			HDMI_RegisterWrite(CTRLI_271_240__DW_0018,0x0);
			HDMI_RegisterWrite(CTRLI_303_272__DW_001C,0xBF0018EE);//PLL from loop 533 3F->18  , 8503 center align
			HDMI_RegisterWrite(CTRLI_335_304__DW_0258,0x000E0090);
			//HDMI_RegisterWrite(CTRLI_375_344__DW_0260,0x691900E0);//Turn RTT_CM  533 00->EO	
			//HDMI_RegisterWrite(CTRLI_375_344__DW_0260,0x69190000);  //Turn RTT_CM  8506 E0->0O
			HDMI_RegisterWrite(CTRLI_375_344__DW_0260,(HDMI_RegisterRead(CTRLI_375_344__DW_0260) & 0x0000ff00) | 0x69190000);  //OFK Calibration setting
			//HDMI_RegisterWrite(CTRLI_407_376__DW_0264,0xDADA1800);
			HDMI_RegisterWrite(CTRLI_407_376__DW_0264,(HDMI_RegisterRead(CTRLI_407_376__DW_0264) & 0x00ff0000) | 0xDA001800);  //OFK Calibration setting
			HDMI_RegisterWrite(CTRLI_439_408__DW_0268,0x5AFABA5A);
			HDMI_RegisterWrite(CTRLI_471_440__DW_026C,0x0A3A3A3A);
			HDMI_RegisterWrite(CTRLI_503_472__DW_0270,0x011F1A0F);
			//HDMI_RegisterWrite(CTRLI_535_504__DW_0274,0x05010101);
			HDMI_RegisterWrite(CTRLI_535_504__DW_0274,0xF0010101);  //HDMIRX_R_SP6~9 = 0
#ifdef USE_HW_ADAPTIVE_EQ
#ifdef CONFIG_HDMI_SUPPORT_MHL
            if((MHL_CABLE_IN == TRUE)&&( DrvHDMIPortSelectBitsGet() == CONFIG_HDMI_MHL_PORT))
            {
    			HDMI_RegisterWrite(CTRLI_567_536__DW_0278,0x23C10F40);
    			//HDMI_RegisterWrite(CTRLI_599_568__DW_027C,0x0F06F023);//HDMIRX_R_SP5_PLL_CTP_PWDJ =1
    			//HDMI_RegisterWrite(CTRLI_599_568__DW_027C,0x0F06E023);//HDMIRX_R_SP5_PLL_CTP_PWDJ =1
    			HDMI_RegisterWrite(CTRLI_599_568__DW_027C,0x0F07C023);  //HDMIRX_R_SP14 = 1
            }
            else
#endif
            {
    			if(bEQ_FIX==0)
    			{
    				bHDMIRX_BS2_0 = 7;
    				//HDMI_RegisterWrite(CTRLI_567_536__DW_0278,0x23C10F40);
    				HDMI_RegisterWrite(CTRLI_567_536__DW_0278,0x03C10F40|(bHDMIRX_BS2_0<<28));
    				//HDMI_RegisterWrite(CTRLI_599_568__DW_027C,0x0F06F023);//HDMIRX_R_SP5_PLL_CTP_PWDJ =1
    				//HDMI_RegisterWrite(CTRLI_599_568__DW_027C,0xF806F023);//HDMIRX_R_SP5_PLL_CTP_PWDJ =1
    				//HDMI_RegisterWrite(CTRLI_599_568__DW_027C,0xF806E023);//HDMIRX_R_SP5_PLL_CTP_PWDJ =1
    				HDMI_RegisterWrite(CTRLI_599_568__DW_027C,0xF807C023);  //HDMIRX_R_SP14 = 1
    			}
    			else
    			{
    				HDMI_RegisterWrite(CTRLI_567_536__DW_0278,0x73C10F40);
    				//HDMI_RegisterWrite(CTRLI_599_568__DW_027C,0xFF06F023);//HDMIRX_R_SP5_PLL_CTP_PWDJ =1
    				//HDMI_RegisterWrite(CTRLI_599_568__DW_027C,0xFF06E023);//HDMIRX_R_SP5_PLL_CTP_PWDJ =1
    				HDMI_RegisterWrite(CTRLI_599_568__DW_027C,0xFF07C023);  //HDMIRX_R_SP14 = 1
    			}
            }
#else
			HDMI_RegisterWrite(CTRLI_567_536__DW_0278,0x23C10F40);
			//HDMI_RegisterWrite(CTRLI_599_568__DW_027C,0x0F06F023);//HDMIRX_R_SP5_PLL_CTP_PWDJ =1
			HDMI_RegisterWrite(CTRLI_599_568__DW_027C,0x0F07D023);  //HDMIRX_R_SP14 = 1
#endif
#ifndef Manu_EQ_Adjust
			//FIX EQ setting
			HDMI_RegisterWrite(CTRLI_631_600__DW_0430,0x24721024);
			HDMI_RegisterWrite(CTRLI_663_632__DW_0434,0x10247210);
#ifdef USE_HW_ADAPTIVE_EQ
			//HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00000072);
#ifdef CONFIG_HDMI_SUPPORT_MHL
            if((MHL_CABLE_IN == TRUE)&&( DrvHDMIPortSelectBitsGet() == CONFIG_HDMI_MHL_PORT))
            {
    			HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00000072);
            }
            else
#endif
            {
                HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00002072|(bHDMIRX_BS3<<16));
            }
#else
			HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00000072);
#endif
#endif			
			break;
		case HDMI_PLL_MODE_HDMI_DISABLE:
			sysset_DEMOD_BG_POWER_DOWN(TRUE);
#ifdef USE_HW_ADAPTIVE_EQ
#ifdef CONFIG_HDMI_SUPPORT_MHL
            if((MHL_CABLE_IN == TRUE)&&( DrvHDMIPortSelectBitsGet() == CONFIG_HDMI_MHL_PORT))
            {
           		HDMI_RegisterWrite(CTRLI_31_0__DW_0280   , 0x00080000);
            }
            else
#endif
            {
                HDMI_RegisterWrite(CTRLI_31_0__DW_0280   , 0x00000000| (bEQ_FIX<<19));
            }
#else
           	HDMI_RegisterWrite(CTRLI_31_0__DW_0280   , 0x00080000);
#endif
			HDMI_RegisterWrite(CTRLI_47_32__DW_0284,0x00000800);
			HDMI_RegisterWrite(CTRLI_79_48__DW_0000,0x00000088  | (bTerm<<4) | bPortSel);
			HDMI_RegisterWrite(CTRLI_111_80__DW_0004,0x0);
			HDMI_RegisterWrite(CTRLI_143_112__DW_0008,0x0);
			HDMI_RegisterWrite(CTRLI_175_144__DW_000C,0x0);
			HDMI_RegisterWrite(CTRLI_207_176__DW_0010,0x0);
			HDMI_RegisterWrite(CTRLI_239_208__DW_0014,0x0);
			HDMI_RegisterWrite(CTRLI_271_240__DW_0018,0x0);
			//HDMI_RegisterWrite(CTRLI_303_272__DW_001C,0x0);
			HDMI_RegisterWrite(CTRLI_335_304__DW_0258,0x80);
			//HDMI_RegisterWrite(CTRLI_375_344__DW_0260,0x40400E0);
//			HDMI_RegisterWrite(CTRLI_375_344__DW_0260,0x4040000);  //Turn RTT_CM  8506 E0->0O
			HDMI_RegisterWrite(CTRLI_375_344__DW_0260,(HDMI_RegisterRead(CTRLI_375_344__DW_0260) & 0x0000ff00) | 0x4040000);  //OFK Calibration setting
//			HDMI_RegisterWrite(CTRLI_407_376__DW_0264,0x0);
			HDMI_RegisterWrite(CTRLI_407_376__DW_0264,(HDMI_RegisterRead(CTRLI_407_376__DW_0264) & 0x00ff0000) | 0x0);  //OFK Calibration setting
			HDMI_RegisterWrite(CTRLI_439_408__DW_0268,0x0);
			HDMI_RegisterWrite(CTRLI_471_440__DW_026C,0x0);
			HDMI_RegisterWrite(CTRLI_503_472__DW_0270,0x0);
			HDMI_RegisterWrite(CTRLI_535_504__DW_0274,0x0);
#ifdef USE_HW_ADAPTIVE_EQ
#ifdef CONFIG_HDMI_SUPPORT_MHL
            if((MHL_CABLE_IN == TRUE)&&( DrvHDMIPortSelectBitsGet() == CONFIG_HDMI_MHL_PORT))
            {
			    HDMI_RegisterWrite(CTRLI_567_536__DW_0278,0x0);
            }
            else
#endif
            {
                HDMI_RegisterWrite(CTRLI_567_536__DW_0278,0x0|(bHDMIRX_BS2_0<<28));
            }
#else
			HDMI_RegisterWrite(CTRLI_567_536__DW_0278,0x0);
#endif
			HDMI_RegisterWrite(CTRLI_599_568__DW_027C,0xF);
			break;
		case HDMI_PLL_MODE_HDMI_FREQ_6:
			//TMDS Clk < 15.6Mhz
			HDMI_RegisterWrite(HDMIRX_EQ_ICTL0, 0x1);
			HDMI_RegisterWrite(HDMIRX_EQ_ICTL1, 0x1);
			HDMI_RegisterWrite(HDMIRX_PHY_IB_CT_CK, 0x3);
			HDMI_RegisterWrite(HDMIRX_PLL_ICTRL_3_0_, 0x5);
			HDMI_RegisterWrite(HDMIRX_PLL_EN_FDIV, 0);
			HDMI_RegisterWrite(HDMIRX_PLL_GB_3_0_, 0x5);
			HDMI_RegisterWrite(HDMIRX_PLL_GB_5_4, 2);//LPF CAP sel
			HDMI_RegisterWrite(HDMIRX_PLL_FEBDIV_7_0_, 79);
            #ifdef HDMI_USE_EXT_DIVSEL
            HDMI_RegisterWrite(HDMIRX_CTL_R_EXT_DIVSEL_EN, 1);
            HDMI_RegisterWrite(HDMIRX_CTL_R_EXT_DIVSEL, 3);
            #else
            HDMI_RegisterWrite(HDMIRX_CTL_R_EXT_DIVSEL_EN, 0);
            #endif
            HDMI_RegisterWrite(HDMIRX_R_SP6, 0);
            HDMI_RegisterWrite(HDMIRX_R_SP7, 0);
            HDMI_RegisterWrite(HDMIRX_R_SP9, 0);
			HDMI_RegisterWrite(HDMIRX_PHY_DIVSLE2, 1);
			HDMI_RegisterWrite(HDMIRX_PLL_DIVSEL2, 1);
			HDMI_RegisterWrite(HDMIRX_PLL_REFDIV, 0);
			HDMI_RegisterWrite(HDMIRX_R_BYTE_ALIGN_CNT2, 4);
            HDMI_RegisterWrite(HDMIRX_ALN_SEL, 0);
            HDMI_RegisterWrite(HDMIRX_de_lo, 0);    //Disable hw adaptive eq condition more stricter
            HDMI_RegisterWrite(HDMIRX_CTL_R_LOCK_CNT_3_0_, 0x8);
			if(HDMI_EQ_MODE_INDEX==HDMI_EQ_INDEX_DEFAULT)
			{
				//HDMI_RegisterWrite(HDMIRX_PHY_EQC0, 7);
				//HDMI_RegisterWrite(HDMIRX_PHY_EQC1, 7);
				//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_0, 1);
				//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_1, 0);
				//HDMI_RegisterWrite(HDMIRX_PHY_EQDC1, 1);
				//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_2, 0);
#ifndef Manu_EQ_Adjust
                if(TRUE == SWITCH_FIX_EQ)
                {
                    HDMI_RegisterWrite(CTRLI_631_600__DW_0430,0x37722037);
                    HDMI_RegisterWrite(CTRLI_663_632__DW_0434,0x20377220);
                }
                else
                {
                    HDMI_RegisterWrite(CTRLI_631_600__DW_0430,0x24721024);
                    HDMI_RegisterWrite(CTRLI_663_632__DW_0434,0x10247210);
                }
#ifdef USE_HW_ADAPTIVE_EQ
#ifdef CONFIG_HDMI_SUPPORT_MHL
                if((MHL_CABLE_IN == TRUE)&&( DrvHDMIPortSelectBitsGet() == CONFIG_HDMI_MHL_PORT))
                {
                    HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00000072);
                }
                else
#endif
                {
    				bHDMIRX_BS3 = 1;
    				bHDMIRX_BS2_0 = 1;      //each eq period :  ~ 17ms
    				HDMI_RegisterWrite(HDMIRX_bs_2_0_, bHDMIRX_BS2_0);
    				//HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00000072);
    				//HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00012072);
    				HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00002072|(bHDMIRX_BS3<<16));
                }
#else
				HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00000072);
#endif
				HDMI_RegisterWrite(HDMIRX_R_SP1_EQ_OUT_VREF0,1);
				HDMI_RegisterWrite(HDMIRX_R_SP1_EQ_OUT_VREF1,1);
				HDMI_RegisterWrite(HDMIRX_BIAS_VREF_SF_SEL_1_0_, 2);
				HDMI_RegisterWrite(HDMIRX_EQ_VDC_SEL, 0);
				HDMI_RegisterWrite(HDMIRX_R_SP2, 1);
				HDMI_RegisterWrite(HDMIRX_R_SP3, 1);
#endif
			}
			else
			{
				HDMI_Set_EQ_Mode(HDMI_EQ_MODE_INDEX);
			}
			HDMI_RegisterWrite(HDMIRX_taps_0, 1);
			HDMI_RegisterWrite(HDMIRX_lowlmt, 1);
			MAX_BCH_ERROR_CNT = 0x80;
			break;
		case HDMI_PLL_MODE_HDMI_FREQ_7_F:
			//18.2Mhz <TMDS Clk < 39Mhz
			HDMI_RegisterWrite(HDMIRX_EQ_ICTL0, 0x1);
			HDMI_RegisterWrite(HDMIRX_EQ_ICTL1, 0x1);
			HDMI_RegisterWrite(HDMIRX_PHY_IB_CT_CK, 0x3);
			HDMI_RegisterWrite(HDMIRX_PLL_ICTRL_3_0_, 0x5);
			HDMI_RegisterWrite(HDMIRX_PLL_EN_FDIV, 0);
			HDMI_RegisterWrite(HDMIRX_PLL_GB_3_0_, 0x5);
			HDMI_RegisterWrite(HDMIRX_PLL_GB_5_4, 2);//LPF CAP sel
			HDMI_RegisterWrite(HDMIRX_PLL_FEBDIV_7_0_, 39);
            #ifdef HDMI_USE_EXT_DIVSEL
            HDMI_RegisterWrite(HDMIRX_CTL_R_EXT_DIVSEL_EN, 1);
            HDMI_RegisterWrite(HDMIRX_CTL_R_EXT_DIVSEL, 3);
            #else
            HDMI_RegisterWrite(HDMIRX_CTL_R_EXT_DIVSEL_EN, 0);
            #endif
            HDMI_RegisterWrite(HDMIRX_R_SP6, 0);
            HDMI_RegisterWrite(HDMIRX_R_SP7, 0);
            HDMI_RegisterWrite(HDMIRX_R_SP9, 0);
			HDMI_RegisterWrite(HDMIRX_PHY_DIVSLE2, 0);
			HDMI_RegisterWrite(HDMIRX_PLL_DIVSEL2, 0);
			HDMI_RegisterWrite(HDMIRX_PLL_REFDIV, 0);
			HDMI_RegisterWrite(HDMIRX_R_BYTE_ALIGN_CNT2, 4);
            HDMI_RegisterWrite(HDMIRX_ALN_SEL, 0);
            HDMI_RegisterWrite(HDMIRX_de_lo, 0);    //Disable hw adaptive eq condition more stricter
            HDMI_RegisterWrite(HDMIRX_CTL_R_LOCK_CNT_3_0_, 0xf);
			if(HDMI_EQ_MODE_INDEX==HDMI_EQ_INDEX_DEFAULT)
			{
				//HDMI_RegisterWrite(HDMIRX_PHY_EQC0, 7);
				//HDMI_RegisterWrite(HDMIRX_PHY_EQC1, 7);
				//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_0, 1);
				//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_1, 1);
				//HDMI_RegisterWrite(HDMIRX_PHY_EQDC1, 3);
				//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_2, 0);
#ifndef Manu_EQ_Adjust
                if(TRUE == SWITCH_FIX_EQ)
                {
                    HDMI_RegisterWrite(CTRLI_631_600__DW_0430,0x37722037);
                    HDMI_RegisterWrite(CTRLI_663_632__DW_0434,0x20377220);
                }
                else
                {
                    HDMI_RegisterWrite(CTRLI_631_600__DW_0430,0x24721024);
                    HDMI_RegisterWrite(CTRLI_663_632__DW_0434,0x10247210);
                }
#ifdef USE_HW_ADAPTIVE_EQ
#ifdef CONFIG_HDMI_SUPPORT_MHL
                if((MHL_CABLE_IN == TRUE)&&( DrvHDMIPortSelectBitsGet() == CONFIG_HDMI_MHL_PORT))
                {
                    HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00000072);
                }
                else
#endif
                {
    				bHDMIRX_BS3 = 1;
    				bHDMIRX_BS2_0 = 0;      //each eq period : 29ms ~ 13ms
    				HDMI_RegisterWrite(HDMIRX_bs_2_0_, bHDMIRX_BS2_0);
    				//HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00000072);
    				//HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00012072);
    				HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00002072|(bHDMIRX_BS3<<16));
                }
#else
				HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00000072);
#endif
				HDMI_RegisterWrite(HDMIRX_R_SP1_EQ_OUT_VREF0,1);
				HDMI_RegisterWrite(HDMIRX_R_SP1_EQ_OUT_VREF1,1);
				HDMI_RegisterWrite(HDMIRX_BIAS_VREF_SF_SEL_1_0_, 2);
				HDMI_RegisterWrite(HDMIRX_EQ_VDC_SEL, 0);
				HDMI_RegisterWrite(HDMIRX_R_SP2, 1);
				HDMI_RegisterWrite(HDMIRX_R_SP3, 1);
#endif
			}
			else
			{
				HDMI_Set_EQ_Mode(HDMI_EQ_MODE_INDEX);
			}
			HDMI_RegisterWrite(HDMIRX_taps_0, 1);
			HDMI_RegisterWrite(HDMIRX_lowlmt, 1);
			MAX_BCH_ERROR_CNT = 0x80;
			break;
		case HDMI_PLL_MODE_HDMI_FREQ_10_1E:
			//41.6Mhz <TMDS Clk < 78Mhz
			HDMI_RegisterWrite(HDMIRX_EQ_ICTL0, 0x1);
			HDMI_RegisterWrite(HDMIRX_EQ_ICTL1, 0x1);
			HDMI_RegisterWrite(HDMIRX_PHY_IB_CT_CK, 0x3);
			HDMI_RegisterWrite(HDMIRX_PLL_ICTRL_3_0_, 0x5);
			HDMI_RegisterWrite(HDMIRX_PLL_EN_FDIV, 0);
			HDMI_RegisterWrite(HDMIRX_PLL_GB_3_0_, 0xb);
			HDMI_RegisterWrite(HDMIRX_PLL_GB_5_4, 2);//LPF CAP sel
			HDMI_RegisterWrite(HDMIRX_PLL_FEBDIV_7_0_, 19);
            #ifdef HDMI_USE_EXT_DIVSEL
            HDMI_RegisterWrite(HDMIRX_CTL_R_EXT_DIVSEL_EN, 1);
            HDMI_RegisterWrite(HDMIRX_CTL_R_EXT_DIVSEL, 2);
            #else
            HDMI_RegisterWrite(HDMIRX_CTL_R_EXT_DIVSEL_EN, 0);
            #endif
            HDMI_RegisterWrite(HDMIRX_R_SP6, 0);
            HDMI_RegisterWrite(HDMIRX_R_SP7, 0);
            HDMI_RegisterWrite(HDMIRX_R_SP9, 0);
			HDMI_RegisterWrite(HDMIRX_PHY_DIVSLE2, 0);
			HDMI_RegisterWrite(HDMIRX_PLL_DIVSEL2, 0);
			HDMI_RegisterWrite(HDMIRX_PLL_REFDIV, 0);
			HDMI_RegisterWrite(HDMIRX_R_BYTE_ALIGN_CNT2, 4);
            HDMI_RegisterWrite(HDMIRX_ALN_SEL, 0);
            HDMI_RegisterWrite(HDMIRX_de_lo, 0);    //Disable hw adaptive eq condition more stricter
            HDMI_RegisterWrite(HDMIRX_CTL_R_LOCK_CNT_3_0_, 0xf);
			if(HDMI_EQ_MODE_INDEX==HDMI_EQ_INDEX_DEFAULT)
			{
				//HDMI_RegisterWrite(HDMIRX_PHY_EQC0, 7);
				//HDMI_RegisterWrite(HDMIRX_PHY_EQC1, 7);
				//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_0, 1);
				//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_1, 0);
				//HDMI_RegisterWrite(HDMIRX_PHY_EQDC1, 1);
				//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_2, 0);
#ifndef Manu_EQ_Adjust
                if(TRUE == SWITCH_FIX_EQ)
                {
                    HDMI_RegisterWrite(CTRLI_631_600__DW_0430,0x37722037);
                    HDMI_RegisterWrite(CTRLI_663_632__DW_0434,0x20377220);
                }
                else
                {
                    HDMI_RegisterWrite(CTRLI_631_600__DW_0430,0x24721024);
                    HDMI_RegisterWrite(CTRLI_663_632__DW_0434,0x10247210);
                }
#ifdef USE_HW_ADAPTIVE_EQ
#ifdef CONFIG_HDMI_SUPPORT_MHL
                if((MHL_CABLE_IN == TRUE)&&( DrvHDMIPortSelectBitsGet() == CONFIG_HDMI_MHL_PORT))
                {
                    HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00000072);
                }
                else
#endif
                {
    				bHDMIRX_BS3 = 0;
    				bHDMIRX_BS2_0 = 7;      //each eq period : 25ms ~ 13ms
    				HDMI_RegisterWrite(HDMIRX_bs_2_0_, bHDMIRX_BS2_0);
    				//HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00000072);
    				//HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00012072);
    				HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00002072|(bHDMIRX_BS3<<16));
                }
#else
				HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00000072);
#endif
				HDMI_RegisterWrite(HDMIRX_R_SP1_EQ_OUT_VREF0,1);
				HDMI_RegisterWrite(HDMIRX_R_SP1_EQ_OUT_VREF1,1);
				HDMI_RegisterWrite(HDMIRX_BIAS_VREF_SF_SEL_1_0_, 2);
				HDMI_RegisterWrite(HDMIRX_EQ_VDC_SEL, 0);
				HDMI_RegisterWrite(HDMIRX_R_SP2, 1);
				HDMI_RegisterWrite(HDMIRX_R_SP3, 1);
#endif
			}
			else
			{
				HDMI_Set_EQ_Mode(HDMI_EQ_MODE_INDEX);
			}
			HDMI_RegisterWrite(HDMIRX_taps_0, 1);
			HDMI_RegisterWrite(HDMIRX_lowlmt, 1);
			MAX_BCH_ERROR_CNT = 0x1000;
			break;		
		case HDMI_PLL_MODE_HDMI_FREQ_1F_32:
			//80.6Mhz <TMDS Clk < 130Mhz
			HDMI_RegisterWrite(HDMIRX_EQ_ICTL0, 0x1);
			HDMI_RegisterWrite(HDMIRX_EQ_ICTL1, 0x1);
			HDMI_RegisterWrite(HDMIRX_PHY_IB_CT_CK, 0x3);
			HDMI_RegisterWrite(HDMIRX_PLL_ICTRL_3_0_, 0x5);
			HDMI_RegisterWrite(HDMIRX_PLL_EN_FDIV, 0);
			HDMI_RegisterWrite(HDMIRX_PLL_GB_3_0_, 0x6);
			HDMI_RegisterWrite(HDMIRX_PLL_GB_5_4, 2);//LPF CAP sel
			HDMI_RegisterWrite(HDMIRX_PLL_FEBDIV_7_0_, 9);
            #ifdef HDMI_USE_EXT_DIVSEL
            HDMI_RegisterWrite(HDMIRX_CTL_R_EXT_DIVSEL_EN, 1);
            HDMI_RegisterWrite(HDMIRX_CTL_R_EXT_DIVSEL, 1);
            #else
            HDMI_RegisterWrite(HDMIRX_CTL_R_EXT_DIVSEL_EN, 0);
            #endif
            HDMI_RegisterWrite(HDMIRX_R_SP6, 0);
            HDMI_RegisterWrite(HDMIRX_R_SP7, 0);
            HDMI_RegisterWrite(HDMIRX_R_SP9, 0);
			HDMI_RegisterWrite(HDMIRX_PHY_DIVSLE2, 0);
			HDMI_RegisterWrite(HDMIRX_PLL_DIVSEL2, 0);
			HDMI_RegisterWrite(HDMIRX_PLL_REFDIV, 0);
			HDMI_RegisterWrite(HDMIRX_R_BYTE_ALIGN_CNT2, 4);
            HDMI_RegisterWrite(HDMIRX_ALN_SEL, 0);
            HDMI_RegisterWrite(HDMIRX_de_lo, 0);    //Disable hw adaptive eq condition more stricter
            HDMI_RegisterWrite(HDMIRX_CTL_R_LOCK_CNT_3_0_, 0xf);
			if(HDMI_EQ_MODE_INDEX==HDMI_EQ_INDEX_DEFAULT)
			{
				//HDMI_RegisterWrite(HDMIRX_PHY_EQC0, 7);
				//HDMI_RegisterWrite(HDMIRX_PHY_EQC1, 7);
				//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_0, 1);
				//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_1, 0);
				//HDMI_RegisterWrite(HDMIRX_PHY_EQDC1, 1);
				//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_2, 0);
#ifndef Manu_EQ_Adjust
                if(TRUE == SWITCH_FIX_EQ)
                {
                    HDMI_RegisterWrite(CTRLI_631_600__DW_0430,0x37722037);
                    HDMI_RegisterWrite(CTRLI_663_632__DW_0434,0x20377220);
                }
                else
                {
                    HDMI_RegisterWrite(CTRLI_631_600__DW_0430,0x24721024);
                    HDMI_RegisterWrite(CTRLI_663_632__DW_0434,0x10247210);
                }
#ifdef USE_HW_ADAPTIVE_EQ
#ifdef CONFIG_HDMI_SUPPORT_MHL
                if((MHL_CABLE_IN == TRUE)&&( DrvHDMIPortSelectBitsGet() == CONFIG_HDMI_MHL_PORT))
                {
                    HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00000072);
                }
                else
#endif
                {
    				bHDMIRX_BS3 = 0;
    				bHDMIRX_BS2_0 = 6;      //each eq period : 26ms ~ 16ms
    				HDMI_RegisterWrite(HDMIRX_bs_2_0_, bHDMIRX_BS2_0);
    				//HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00000072);
    				//HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00012072);
    				HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00002072|(bHDMIRX_BS3<<16));
                }
#else
				HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00000072);
#endif
				HDMI_RegisterWrite(HDMIRX_R_SP1_EQ_OUT_VREF0,1);
				HDMI_RegisterWrite(HDMIRX_R_SP1_EQ_OUT_VREF1,1);
				HDMI_RegisterWrite(HDMIRX_BIAS_VREF_SF_SEL_1_0_, 2);
				HDMI_RegisterWrite(HDMIRX_EQ_VDC_SEL, 0);
				HDMI_RegisterWrite(HDMIRX_R_SP2, 1);
				HDMI_RegisterWrite(HDMIRX_R_SP3, 1);
#endif
			}
			else
			{
				HDMI_Set_EQ_Mode(HDMI_EQ_MODE_INDEX);
			}
			HDMI_RegisterWrite(HDMIRX_taps_0, 1);
			HDMI_RegisterWrite(HDMIRX_lowlmt, 1);
			MAX_BCH_ERROR_CNT = 0x1800;
			break;
		case HDMI_PLL_MODE_HDMI_FREQ_33_3D:
			//132.6Mhz <TMDS Clk < 158.6Mhz
			HDMI_RegisterWrite(HDMIRX_EQ_ICTL0, 0x1);
			HDMI_RegisterWrite(HDMIRX_EQ_ICTL1, 0x1);
			HDMI_RegisterWrite(HDMIRX_PHY_IB_CT_CK, 0x3);
			HDMI_RegisterWrite(HDMIRX_PLL_ICTRL_3_0_, 0x5);
			HDMI_RegisterWrite(HDMIRX_PLL_EN_FDIV, 0);
			HDMI_RegisterWrite(HDMIRX_PLL_GB_3_0_, 0xc);
			HDMI_RegisterWrite(HDMIRX_PLL_GB_5_4, 2);//LPF CAP sel
			HDMI_RegisterWrite(HDMIRX_PLL_FEBDIV_7_0_, 9);
            #ifdef HDMI_USE_EXT_DIVSEL
            HDMI_RegisterWrite(HDMIRX_CTL_R_EXT_DIVSEL_EN, 1);
            HDMI_RegisterWrite(HDMIRX_CTL_R_EXT_DIVSEL, 1);
            #else
            HDMI_RegisterWrite(HDMIRX_CTL_R_EXT_DIVSEL_EN, 0);
            #endif
            HDMI_RegisterWrite(HDMIRX_R_SP6, 0);
            HDMI_RegisterWrite(HDMIRX_R_SP7, 0);
            HDMI_RegisterWrite(HDMIRX_R_SP9, 0);
			HDMI_RegisterWrite(HDMIRX_PHY_DIVSLE2, 0);
			HDMI_RegisterWrite(HDMIRX_PLL_DIVSEL2, 0);
			HDMI_RegisterWrite(HDMIRX_PLL_REFDIV, 0);
			HDMI_RegisterWrite(HDMIRX_R_BYTE_ALIGN_CNT2, 4);
            HDMI_RegisterWrite(HDMIRX_ALN_SEL, 0);
            HDMI_RegisterWrite(HDMIRX_de_lo, 0);    //Disable hw adaptive eq condition more stricter
            HDMI_RegisterWrite(HDMIRX_CTL_R_LOCK_CNT_3_0_, 0xf);
			if(HDMI_EQ_MODE_INDEX==HDMI_EQ_INDEX_DEFAULT)
			{
				//HDMI_RegisterWrite(HDMIRX_PHY_EQC0, 7);
				//HDMI_RegisterWrite(HDMIRX_PHY_EQC1, 7);
				//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_0, 1);
				//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_1, 0);
				//HDMI_RegisterWrite(HDMIRX_PHY_EQDC1, 1);
				//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_2, 0);
#ifndef Manu_EQ_Adjust
                if(TRUE == SWITCH_FIX_EQ)
                {
                    HDMI_RegisterWrite(CTRLI_631_600__DW_0430,0x37722037);
                    HDMI_RegisterWrite(CTRLI_663_632__DW_0434,0x20377220);
                }
                else
                {
                    HDMI_RegisterWrite(CTRLI_631_600__DW_0430,0x24721024);
                    HDMI_RegisterWrite(CTRLI_663_632__DW_0434,0x10247210);
                }
#ifdef USE_HW_ADAPTIVE_EQ
#ifdef CONFIG_HDMI_SUPPORT_MHL
                if((MHL_CABLE_IN == TRUE)&&( DrvHDMIPortSelectBitsGet() == CONFIG_HDMI_MHL_PORT))
                {
                    HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00000072);
                }
                else
#endif
                {
    				bHDMIRX_BS3 = 0;
    				bHDMIRX_BS2_0 = 5;      //each eq period : 32ms ~ 27ms
    				HDMI_RegisterWrite(HDMIRX_bs_2_0_, bHDMIRX_BS2_0);
    				//HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00000072);
    				//HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00012072);
    				HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00002072|(bHDMIRX_BS3<<16));
                }
#else
				HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00000072);
#endif
				HDMI_RegisterWrite(HDMIRX_R_SP1_EQ_OUT_VREF0,1);
				HDMI_RegisterWrite(HDMIRX_R_SP1_EQ_OUT_VREF1,1);
				HDMI_RegisterWrite(HDMIRX_BIAS_VREF_SF_SEL_1_0_, 2);
				HDMI_RegisterWrite(HDMIRX_EQ_VDC_SEL, 0);
				HDMI_RegisterWrite(HDMIRX_R_SP2, 1);
				HDMI_RegisterWrite(HDMIRX_R_SP3, 1);
#endif
			}
			else
			{
				HDMI_Set_EQ_Mode(HDMI_EQ_MODE_INDEX);
			}
			HDMI_RegisterWrite(HDMIRX_taps_0, 1);
			HDMI_RegisterWrite(HDMIRX_lowlmt, 1);
			MAX_BCH_ERROR_CNT = 0x1800;
			break;
		case HDMI_PLL_MODE_HDMI_FREQ_3E_60:
			//161.2Mhz <TMDS Clk < 249.6Mhz
			HDMI_RegisterWrite(HDMIRX_EQ_ICTL0, 0x1);
			HDMI_RegisterWrite(HDMIRX_EQ_ICTL1, 0x1);
			HDMI_RegisterWrite(HDMIRX_PHY_IB_CT_CK, 0x3);
			HDMI_RegisterWrite(HDMIRX_PLL_ICTRL_3_0_, 0x5);
			HDMI_RegisterWrite(HDMIRX_PLL_EN_FDIV, 0);
			HDMI_RegisterWrite(HDMIRX_PLL_GB_3_0_, 0x6);
			HDMI_RegisterWrite(HDMIRX_PLL_GB_5_4, 2);//LPF CAP sel
			HDMI_RegisterWrite(HDMIRX_PLL_FEBDIV_7_0_, 4);
            #ifdef HDMI_USE_EXT_DIVSEL
            HDMI_RegisterWrite(HDMIRX_CTL_R_EXT_DIVSEL_EN, 1);
            HDMI_RegisterWrite(HDMIRX_CTL_R_EXT_DIVSEL, 0);
            #else
            HDMI_RegisterWrite(HDMIRX_CTL_R_EXT_DIVSEL_EN, 0);
            #endif
            HDMI_RegisterWrite(HDMIRX_R_SP6, 0);
            HDMI_RegisterWrite(HDMIRX_R_SP7, 0);
            HDMI_RegisterWrite(HDMIRX_R_SP9, 0);
            
			HDMI_RegisterWrite(HDMIRX_PHY_DIVSLE2, 0);
			HDMI_RegisterWrite(HDMIRX_PLL_DIVSEL2, 0);
			HDMI_RegisterWrite(HDMIRX_PLL_REFDIV, 0);
			HDMI_RegisterWrite(HDMIRX_R_BYTE_ALIGN_CNT2, 4);
            HDMI_RegisterWrite(HDMIRX_ALN_SEL, 0);
            HDMI_RegisterWrite(HDMIRX_de_lo, 0);    //Disable hw adaptive eq condition more stricter
            HDMI_RegisterWrite(HDMIRX_CTL_R_LOCK_CNT_3_0_, 0xf);
			if(HDMI_EQ_MODE_INDEX==HDMI_EQ_INDEX_DEFAULT)
			{
				//HDMI_RegisterWrite(HDMIRX_PHY_EQC0, 4);
				//HDMI_RegisterWrite(HDMIRX_PHY_EQC1, 4);
				//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_0, 1);
				//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_1, 0);
				//HDMI_RegisterWrite(HDMIRX_PHY_EQDC1, 1);
				//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_2, 0);
#ifndef Manu_EQ_Adjust
                if(TRUE == SWITCH_FIX_EQ)
                {
                    HDMI_RegisterWrite(CTRLI_631_600__DW_0430,0x37722037);
                    HDMI_RegisterWrite(CTRLI_663_632__DW_0434,0x20377220);
                }
                else
                {
                    HDMI_RegisterWrite(CTRLI_631_600__DW_0430,0x24721024);
                    HDMI_RegisterWrite(CTRLI_663_632__DW_0434,0x10247210);
                }
#ifdef USE_HW_ADAPTIVE_EQ
#ifdef CONFIG_HDMI_SUPPORT_MHL
                if((MHL_CABLE_IN == TRUE)&&( DrvHDMIPortSelectBitsGet() == CONFIG_HDMI_MHL_PORT))
                {
                    HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00000072);
                }
                else
#endif
                {
    				bHDMIRX_BS3 = 0;
    				bHDMIRX_BS2_0 = 5;      //each eq period : 26ms ~ 17ms
    				HDMI_RegisterWrite(HDMIRX_bs_2_0_, bHDMIRX_BS2_0);
    				//HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00000072);
    				//HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00012072);
    				HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00002072|(bHDMIRX_BS3<<16));
                }
#else
				HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00000072);
#endif
				HDMI_RegisterWrite(HDMIRX_R_SP1_EQ_OUT_VREF0,1);
				HDMI_RegisterWrite(HDMIRX_R_SP1_EQ_OUT_VREF1,1);
				HDMI_RegisterWrite(HDMIRX_BIAS_VREF_SF_SEL_1_0_, 2);
				HDMI_RegisterWrite(HDMIRX_EQ_VDC_SEL, 0);
				HDMI_RegisterWrite(HDMIRX_R_SP2, 1);
				HDMI_RegisterWrite(HDMIRX_R_SP3, 1);
#endif
			}
			else
			{
				HDMI_Set_EQ_Mode(HDMI_EQ_MODE_INDEX);
			}
			HDMI_RegisterWrite(HDMIRX_taps_0, 0);
			HDMI_RegisterWrite(HDMIRX_lowlmt, 0);
			MAX_BCH_ERROR_CNT = 0x3200;
			break;
		case HDMI_PLL_MODE_HDMI_FREQ_61:
			//252.2Mhz <TMDS Clk 
			HDMI_RegisterWrite(HDMIRX_EQ_ICTL0, 0x1);
			HDMI_RegisterWrite(HDMIRX_EQ_ICTL1, 0x1);
			HDMI_RegisterWrite(HDMIRX_PHY_IB_CT_CK, 0x3);
			//HDMI_RegisterWrite(HDMIRX_PLL_ICTRL_3_0_, 0xC);
			HDMI_RegisterWrite(HDMIRX_PLL_ICTRL_3_0_, 0x5);
			//HDMI_RegisterWrite(HDMIRX_PLL_ICTRL_3_0_, 0x7);
			HDMI_RegisterWrite(HDMIRX_PLL_EN_FDIV, 0);
			HDMI_RegisterWrite(HDMIRX_PLL_GB_3_0_, 0xa);
			//HDMI_RegisterWrite(HDMIRX_PLL_GB_5_4, 0);//LPF CAP sel
			HDMI_RegisterWrite(HDMIRX_PLL_GB_5_4, 2);//LPF CAP sel
			HDMI_RegisterWrite(HDMIRX_PLL_FEBDIV_7_0_, 4);
            #ifdef HDMI_USE_EXT_DIVSEL
            HDMI_RegisterWrite(HDMIRX_CTL_R_EXT_DIVSEL_EN, 1);
            HDMI_RegisterWrite(HDMIRX_CTL_R_EXT_DIVSEL, 0);
            #else
            HDMI_RegisterWrite(HDMIRX_CTL_R_EXT_DIVSEL_EN, 0);
            #endif
            HDMI_RegisterWrite(HDMIRX_R_SP6, 0);
            HDMI_RegisterWrite(HDMIRX_R_SP7, 0);
            HDMI_RegisterWrite(HDMIRX_R_SP9, 0);

			HDMI_RegisterWrite(HDMIRX_PHY_DIVSLE2, 0);
			HDMI_RegisterWrite(HDMIRX_PLL_DIVSEL2, 0);
			//HDMI_RegisterWrite(HDMIRX_PLL_REFDIV, 1);
			HDMI_RegisterWrite(HDMIRX_PLL_REFDIV, 0);
			HDMI_RegisterWrite(HDMIRX_R_BYTE_ALIGN_CNT2, 4);
            HDMI_RegisterWrite(HDMIRX_ALN_SEL, 1);
            HDMI_RegisterWrite(HDMIRX_de_lo, 0);    //Disable hw adaptive eq condition more stricter
            HDMI_RegisterWrite(HDMIRX_CTL_R_LOCK_CNT_3_0_, 0xf);
			if(HDMI_EQ_MODE_INDEX==HDMI_EQ_INDEX_DEFAULT)
			{
				//HDMI_RegisterWrite(HDMIRX_PHY_EQC0, 4);
				//HDMI_RegisterWrite(HDMIRX_PHY_EQC1, 4);
				//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_0, 1);
				//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_1, 0);
				//HDMI_RegisterWrite(HDMIRX_PHY_EQDC1, 1);
				//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_2, 0);
#ifndef Manu_EQ_Adjust
                if(TRUE == SWITCH_FIX_EQ)
                {
                    HDMI_RegisterWrite(CTRLI_631_600__DW_0430,0x37722037);
                    HDMI_RegisterWrite(CTRLI_663_632__DW_0434,0x20377220);
                }
                else
                {
                    HDMI_RegisterWrite(CTRLI_631_600__DW_0430,0x24721024);
                    HDMI_RegisterWrite(CTRLI_663_632__DW_0434,0x10247210);
                }
#ifdef USE_HW_ADAPTIVE_EQ
#ifdef CONFIG_HDMI_SUPPORT_MHL
                if((MHL_CABLE_IN == TRUE)&&( DrvHDMIPortSelectBitsGet() == CONFIG_HDMI_MHL_PORT))
                {
                    HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00000072);
                }
                else
#endif
                {
    				bHDMIRX_BS3 = 0;
    				bHDMIRX_BS2_0 = 4;      //each eq period : 33ms
    				HDMI_RegisterWrite(HDMIRX_bs_2_0_, bHDMIRX_BS2_0);
    				//HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00000072);
    				//HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00012072);
    				HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00002072|(bHDMIRX_BS3<<16));
                }
#else
				HDMI_RegisterWrite(CTRLI_695_664__DW_0438,0x00000072);
#endif
				HDMI_RegisterWrite(HDMIRX_R_SP1_EQ_OUT_VREF0,1);
				HDMI_RegisterWrite(HDMIRX_R_SP1_EQ_OUT_VREF1,1);
				HDMI_RegisterWrite(HDMIRX_BIAS_VREF_SF_SEL_1_0_, 2);
				HDMI_RegisterWrite(HDMIRX_EQ_VDC_SEL, 0);
				HDMI_RegisterWrite(HDMIRX_R_SP2, 1);
				HDMI_RegisterWrite(HDMIRX_R_SP3, 1);
#endif
			}
			else
			{
				HDMI_Set_EQ_Mode(HDMI_EQ_MODE_INDEX);
			}
			HDMI_RegisterWrite(HDMIRX_taps_0, 0);
			HDMI_RegisterWrite(HDMIRX_lowlmt, 0);
			MAX_BCH_ERROR_CNT = 0x3200;
			break;
		/* DEMOD */
        case HDMI_PLL_MODE_ADEMOD_INIT:
            HDMI_RegisterWrite(CTRLI_31_0__DW_0280   , 0x00080000);
            HDMI_RegisterWrite(CTRLI_47_32__DW_0284  , 0x00000106);//0
            HDMI_RegisterWrite(CTRLI_79_48__DW_0000  , 0x00001080  | (bTerm<<4));
            HDMI_RegisterWrite(CTRLI_111_80__DW_0004 , 0x00000000);
            HDMI_RegisterWrite(CTRLI_143_112__DW_0008, 0x00000000);
            HDMI_RegisterWrite(CTRLI_175_144__DW_000C, 0x00000000);
            HDMI_RegisterWrite(CTRLI_207_176__DW_0010, 0x00000000);
            HDMI_RegisterWrite(CTRLI_239_208__DW_0014, 0x00000000);
            HDMI_RegisterWrite(CTRLI_271_240__DW_0018, 0x00000000);
            HDMI_RegisterWrite(CTRLI_303_272__DW_001C, 0x00000000);
            HDMI_RegisterWrite(CTRLI_335_304__DW_0258, 0x40040000);
            //HDMI_RegisterWrite(CTRLI_375_344__DW_0260, 0x000000E0);
            HDMI_RegisterWrite(CTRLI_375_344__DW_0260, 0x00000000);  //Turn RTT_CM  8506 E0->0O
            HDMI_RegisterWrite(CTRLI_407_376__DW_0264, 0x00000000);
            HDMI_RegisterWrite(CTRLI_439_408__DW_0268, 0x00000000);
            HDMI_RegisterWrite(CTRLI_471_440__DW_026C, 0x00000000);
            HDMI_RegisterWrite(CTRLI_503_472__DW_0270, 0x00000000);
            //HDMI_RegisterWrite(CTRLI_535_504__DW_0274, 0x00000000);
            HDMI_RegisterWrite(CTRLI_535_504__DW_0274, 0xF0000000);
            HDMI_RegisterWrite(CTRLI_567_536__DW_0278, 0x00000000);
            HDMI_RegisterWrite(CTRLI_599_568__DW_027C, 0x00000000);
            HDMI_RegisterWrite(HDMIRX_HDMIP0_MHL_Mode_Sel_external,0x0);
            HDMI_RegisterWrite(HDMIRX_HDMIP0_MHL_Mode_Sel_mux,0x0);
            HDMI_RegisterWrite(HDMIRX_HDMIP0_MHL_Mode_PLL_Sel_external,0x0);
            HDMI_RegisterWrite(HDMIRX_HDMIP0_MHL_Mode_Sel_PLL_mux,0x0);
            HDMI_RegisterWrite(HDMIRX_TMDSCLK_PP_SEL, 0x1);
            HDMI_RegisterWrite(HDMIRX_external_gated_TMDSCLK, 0x1);			
            HDMI_DelayMs(1);
            break;
        case HDMI_PLL_MODE_ADEMOD_ENABLE:
            sysset_DEMOD_BG_POWER_DOWN(FALSE);
            HDMI_RegisterWrite(HDMIRX_HDMIP0_MHL_Mode_Sel_external,0x0);
            HDMI_RegisterWrite(HDMIRX_HDMIP0_MHL_Mode_Sel_mux,0x0);
            HDMI_RegisterWrite(HDMIRX_HDMIP0_MHL_Mode_PLL_Sel_external,0x0);
            HDMI_RegisterWrite(HDMIRX_HDMIP0_MHL_Mode_Sel_PLL_mux,0x0);
            HDMI_RegisterWrite(HDMIRX_TMDSCLK_PP_SEL, 0x1);
            HDMI_RegisterWrite(HDMIRX_external_gated_TMDSCLK, 0x1);
			
            HDMI_RegisterWrite(HDMIRX_COMP_PD, 0x0);
            HDMI_RegisterWrite(HDMIRX_PLL_PD_COMP, 0x0);

            //HDMI_RegisterWrite(HDMIRX_PLL_ICTRL_3_0_, 0x6);
            HDMI_RegisterWrite(HDMIRX_PLL_ICTRL_3_0_, 0x1);
            HDMI_RegisterWrite(HDMIRX_PLL_EN_FDIV, 0x0);//For ATV Line Noise
            HDMI_RegisterWrite(HDMIRX_PLL_GB_5_4, 0);//LPF CAP sel
            //HDMI_RegisterWrite(HDMIRX_PLL_GB_4_0_, 0x3);// 3
            HDMI_RegisterWrite(HDMIRX_PLL_GB_3_0_, 0xf);// 3
            HDMI_RegisterWrite(HDMIRX_PLL_FEBDIV_7_0_, 0x2f);
			
            HDMI_RegisterWrite(HDMIRX_PHY_DIVSLE2, 0x1);
            HDMI_RegisterWrite(HDMIRX_PDACJ_CK, 0x1);
            HDMI_DelayUs(1); //PLL_Power need 500 nsec to stable

            //HDMI_RegisterWrite(HDMIRX_PLL_RESETJ, 0x1);
            //HDMI_DelayMs(1);

            HDMI_RegisterWrite(HDMIRX_PLL_PWDN_DEMOD, 0x1);
            HDMI_RegisterWrite(HDMIRX_PLL_RSTN, 0x1);
            HDMI_RegisterWrite(HDMIRX_PLL_PWDN_DEMOD, 0x1);
	     	HDMI_DelayUs(1);

            HDMI_RegisterWrite(HDMIRX_R_SP5_PLL_CTP_PWDJ, 0x1);
            HDMI_RegisterWrite(HDMIRX_LDO_PWD, 0x1);// 1/0 : normal / PD (change define from 331)
            HDMI_RegisterWrite(HDMIRX_LDO_PWDE, 0x1);// 1/0 : normal / PD (change define from 331)
            HDMI_DelayUs(8);
            HDMI_RegisterWrite(HDMIRX_PLL_PWDN_DEMOD, 0x0);
            HDMI_DelayUs(1);
            HDMI_RegisterWrite(HDMIRX_PLL_PWDN_DEMOD, 0x1);
            HDMI_DelayUs(1);

			
            HDMI_RegisterWrite(HDMIRX_PLL_RESETJ, 0x1);
            HDMI_DelayUs(1);

            HDMI_RegisterWrite(HDMIRX_PLL_EN_FDIV, 0x0);//For ATV Line Noise
            HDMI_RegisterWrite(HDMIRX_PLL_GB_3_0_, 0x3);// 3
            HDMI_RegisterWrite(HDMIRX_PLL_ICTRL_3_0_, 0x6);
			
            break;
        case HDMI_PLL_MODE_ADEMOD_DISABLE:
            sysset_DEMOD_BG_POWER_DOWN(TRUE);
            HDMI_RegisterWrite(CTRLI_31_0__DW_0280, 0x000c0400);
            HDMI_RegisterWrite(CTRLI_47_32__DW_0284, 0x00000006);
            HDMI_RegisterWrite(CTRLI_79_48__DW_0000, 0x00000088  | (bTerm<<4));
            HDMI_RegisterWrite(CTRLI_111_80__DW_0004, 0x00000000);
            HDMI_RegisterWrite(CTRLI_143_112__DW_0008, 0x00000000);
            HDMI_RegisterWrite(CTRLI_175_144__DW_000C, 0x00000000);
            HDMI_RegisterWrite(CTRLI_207_176__DW_0010, 0x00000000);
            HDMI_RegisterWrite(CTRLI_239_208__DW_0014, 0x00000000);
            HDMI_RegisterWrite(CTRLI_271_240__DW_0018, 0x00000000);
            HDMI_RegisterWrite(CTRLI_303_272__DW_001C, 0x71da0000);
            HDMI_RegisterWrite(CTRLI_335_304__DW_0258, 0x40040010);
            //HDMI_RegisterWrite(CTRLI_375_344__DW_0260, 0x71da00E0);
            HDMI_RegisterWrite(CTRLI_375_344__DW_0260, 0x71da0000);  //Turn RTT_CM  8506 E0->0O
            HDMI_RegisterWrite(CTRLI_439_408__DW_0268, 0x00000000);
            HDMI_RegisterWrite(CTRLI_471_440__DW_026C, 0x00000000);
            HDMI_RegisterWrite(CTRLI_503_472__DW_0270, 0x00000000);
            HDMI_RegisterWrite(CTRLI_535_504__DW_0274, 0x00000000);
            HDMI_RegisterWrite(CTRLI_567_536__DW_0278, 0x00000000);
            HDMI_RegisterWrite(CTRLI_599_568__DW_027C, 0x00000000);
            HDMI_DelayMs(1);
            break;
        case HDMI_PLL_MODE_DDEMOD_INIT:
            HDMI_RegisterWrite(CTRLI_31_0__DW_0280   , 0x00080000);
            HDMI_RegisterWrite(CTRLI_47_32__DW_0284  , 0x00000106);
            HDMI_RegisterWrite(CTRLI_79_48__DW_0000  , 0x00001080  | (bTerm<<4));
            HDMI_RegisterWrite(CTRLI_111_80__DW_0004 , 0x00000000);
            HDMI_RegisterWrite(CTRLI_143_112__DW_0008, 0x00000000);
            HDMI_RegisterWrite(CTRLI_175_144__DW_000C, 0x00000000);
            HDMI_RegisterWrite(CTRLI_207_176__DW_0010, 0x00000000);
            HDMI_RegisterWrite(CTRLI_239_208__DW_0014, 0x00000000);
            HDMI_RegisterWrite(CTRLI_271_240__DW_0018, 0x00000000);
            HDMI_RegisterWrite(CTRLI_303_272__DW_001C, 0x00000000);
            HDMI_RegisterWrite(CTRLI_335_304__DW_0258, 0x40040000);
            //HDMI_RegisterWrite(CTRLI_375_344__DW_0260, 0x000000E0);
            HDMI_RegisterWrite(CTRLI_375_344__DW_0260, 0x00000000);  //Turn RTT_CM  8506 E0->0O
            HDMI_RegisterWrite(CTRLI_407_376__DW_0264, 0x00000000);
            HDMI_RegisterWrite(CTRLI_439_408__DW_0268, 0x00000000);
            HDMI_RegisterWrite(CTRLI_471_440__DW_026C, 0x00000000);
            HDMI_RegisterWrite(CTRLI_503_472__DW_0270, 0x00000000);
            //HDMI_RegisterWrite(CTRLI_535_504__DW_0274, 0x00000000);
            HDMI_RegisterWrite(CTRLI_535_504__DW_0274, 0xF0000000);
            HDMI_RegisterWrite(CTRLI_567_536__DW_0278, 0x00000000);
            HDMI_RegisterWrite(CTRLI_599_568__DW_027C, 0x00000000);
            HDMI_RegisterWrite(HDMIRX_HDMIP0_MHL_Mode_Sel_external,0x0);
            HDMI_RegisterWrite(HDMIRX_HDMIP0_MHL_Mode_Sel_mux,0x0);
            HDMI_RegisterWrite(HDMIRX_HDMIP0_MHL_Mode_PLL_Sel_external,0x0);
            HDMI_RegisterWrite(HDMIRX_HDMIP0_MHL_Mode_Sel_PLL_mux,0x0);
            HDMI_RegisterWrite(HDMIRX_TMDSCLK_PP_SEL, 0x1);
            HDMI_RegisterWrite(HDMIRX_external_gated_TMDSCLK, 0x1);
            HDMI_DelayMs(1);
            break;
        case HDMI_PLL_MODE_DDEMOD_ENABLE_LDO_SETTING:
            sysset_DEMOD_BG_POWER_DOWN(FALSE);
            HDMI_RegisterWrite(HDMIRX_HDMIP0_MHL_Mode_Sel_external,0x0);
            HDMI_RegisterWrite(HDMIRX_HDMIP0_MHL_Mode_Sel_mux,0x0);
            HDMI_RegisterWrite(HDMIRX_HDMIP0_MHL_Mode_PLL_Sel_external,0x0);
            HDMI_RegisterWrite(HDMIRX_HDMIP0_MHL_Mode_Sel_PLL_mux,0x0);
            HDMI_RegisterWrite(HDMIRX_TMDSCLK_PP_SEL, 0x1);
            HDMI_RegisterWrite(HDMIRX_external_gated_TMDSCLK, 0x1);
			
            HDMI_RegisterWrite(HDMIRX_COMP_PD, 0x0);
            HDMI_RegisterWrite(HDMIRX_PLL_PD_COMP, 0x0);

            //HDMI_RegisterWrite(HDMIRX_PLL_ICTRL_3_0_, 0x6);
            HDMI_RegisterWrite(HDMIRX_PLL_ICTRL_3_0_, 0x1);
            HDMI_RegisterWrite(HDMIRX_PLL_EN_FDIV, 0x0);
            HDMI_RegisterWrite(HDMIRX_PLL_GB_5_4, 0);//LPF CAP sel
            //HDMI_RegisterWrite(HDMIRX_PLL_GB_4_0_, 0x3);//6->3  
            HDMI_RegisterWrite(HDMIRX_PLL_GB_3_0_, 0xf);//6->3  
            HDMI_RegisterWrite(HDMIRX_PLL_FEBDIV_7_0_, 0x2f);
			
            HDMI_RegisterWrite(HDMIRX_PHY_DIVSLE2, 0x1);
            HDMI_RegisterWrite(HDMIRX_PDACJ_CK, 0x1);
            HDMI_DelayUs(1); //PLL_Power need 500 nsec to stable

           // HDMI_RegisterWrite(HDMIRX_PLL_RESETJ, 0x1);
           // HDMI_DelayMs(1);

            HDMI_RegisterWrite(HDMIRX_PLL_PWDN_DEMOD, 0x1);
            HDMI_RegisterWrite(HDMIRX_PLL_RSTN, 0x1);
            HDMI_RegisterWrite(HDMIRX_PLL_PWDN_DEMOD, 0x1);
	     	HDMI_DelayUs(1);

            HDMI_RegisterWrite(HDMIRX_R_SP5_PLL_CTP_PWDJ, 0x1);
            HDMI_RegisterWrite(HDMIRX_LDO_PWD, 0x1);// 1/0 : normal / PD (change define from 331)
            HDMI_RegisterWrite(HDMIRX_LDO_PWDE, 0x1);// 1/0 : normal / PD (change define from 331)
            HDMI_DelayUs(8);
            HDMI_RegisterWrite(HDMIRX_PLL_PWDN_DEMOD, 0x0);
            HDMI_DelayUs(1);
            HDMI_RegisterWrite(HDMIRX_PLL_PWDN_DEMOD, 0x1);
            HDMI_DelayUs(1);

			
            HDMI_RegisterWrite(HDMIRX_PLL_RESETJ, 0x1);
            HDMI_DelayUs(1);

            HDMI_RegisterWrite(HDMIRX_PLL_EN_FDIV, 0x0);//
            HDMI_RegisterWrite(HDMIRX_PLL_GB_3_0_, 0x3);// 3
            HDMI_RegisterWrite(HDMIRX_PLL_ICTRL_3_0_, 0x6);
			

            break;
        case HDMI_PLL_MODE_DDEMOD_DISABLE:
            sysset_DEMOD_BG_POWER_DOWN(TRUE);
            HDMI_RegisterWrite(CTRLI_31_0__DW_0280   , 0x00000000);
            HDMI_RegisterWrite(CTRLI_47_32__DW_0284  , 0x00000106);
            HDMI_RegisterWrite(CTRLI_79_48__DW_0000  , 0x00001088  | (bTerm<<4));
            HDMI_RegisterWrite(CTRLI_111_80__DW_0004 , 0x00000000);
            HDMI_RegisterWrite(CTRLI_143_112__DW_0008, 0x00000000);
            HDMI_RegisterWrite(CTRLI_175_144__DW_000C, 0x00000000);
            HDMI_RegisterWrite(CTRLI_207_176__DW_0010, 0x00000000);
            HDMI_RegisterWrite(CTRLI_239_208__DW_0014, 0x00000000);
            HDMI_RegisterWrite(CTRLI_271_240__DW_0018, 0x00000000);
            HDMI_RegisterWrite(CTRLI_303_272__DW_001C, 0x00000000);
            HDMI_RegisterWrite(CTRLI_335_304__DW_0258, 0x40040000);
            HDMI_RegisterWrite(CTRLI_375_344__DW_0260, 0x00000000);
            HDMI_RegisterWrite(CTRLI_407_376__DW_0264, 0x00000000);
            HDMI_RegisterWrite(CTRLI_439_408__DW_0268, 0x00000000);
            HDMI_RegisterWrite(CTRLI_471_440__DW_026C, 0x00000000);
            HDMI_RegisterWrite(CTRLI_503_472__DW_0270, 0x00000000);
            HDMI_RegisterWrite(CTRLI_535_504__DW_0274, 0x00000000);
            HDMI_RegisterWrite(CTRLI_567_536__DW_0278, 0x00000000);
            HDMI_RegisterWrite(CTRLI_599_568__DW_027C, 0x00000000);
            HDMI_DelayMs(1);
            break;
		/* DEFAULT */
		default:
			printk("[H] mode is not exist\n");
			break;
	}
}

//set HDMI EQ Mode
void HDMI_Set_EQ_Mode(HDMI_EQ_INDEX_e eHDMI_EQ_MODE)
{

	printk("[H] %s mode:%d\n", __FUNCTION__, eHDMI_EQ_MODE);

	switch(eHDMI_EQ_MODE)
	{
		/* Default */
		case HDMI_EQ_INDEX_DEFAULT:
			HDMI_EQ_MODE_INDEX =eHDMI_EQ_MODE ;	
			break;
			
		case HDMI_EQ_INDEX_1:
			//HDMI_RegisterWrite(HDMIRX_PHY_EQC0, 7);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQC1, 7);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_0, 1);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_1, 1);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQDC1, 1);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_2, 1);
			HDMI_EQ_MODE_INDEX =eHDMI_EQ_MODE ;	
			break;
			
		case HDMI_EQ_INDEX_2:
			//HDMI_RegisterWrite(HDMIRX_PHY_EQC0, 7);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQC1, 7);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_0, 1);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_1, 0);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQDC1, 7);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_2, 0);
			HDMI_EQ_MODE_INDEX =eHDMI_EQ_MODE ;	
			break;
			
		case HDMI_EQ_INDEX_3:
			//HDMI_RegisterWrite(HDMIRX_PHY_EQC0, 0);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQC1, 0);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_0, 1);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_1, 1);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQDC1, 7);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_2, 1);
			HDMI_EQ_MODE_INDEX =eHDMI_EQ_MODE ;	
			break;
			
		case HDMI_EQ_INDEX_4:
			//HDMI_RegisterWrite(HDMIRX_PHY_EQC0, 1);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQC1, 1);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_0, 1);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_1, 1);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQDC1, 3);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_2, 0);
			HDMI_EQ_MODE_INDEX =eHDMI_EQ_MODE ;	
			break;
			
		case HDMI_EQ_INDEX_5:
			//HDMI_RegisterWrite(HDMIRX_PHY_EQC0, 4);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQC1, 4);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_0, 1);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_1, 1);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQDC1, 3);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_2, 0);
			HDMI_EQ_MODE_INDEX =eHDMI_EQ_MODE ;	
			break;
			
		case HDMI_EQ_INDEX_6:
			//HDMI_RegisterWrite(HDMIRX_PHY_EQC0, 7);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQC1, 7);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_0, 1);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_1, 1);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQDC1, 1);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_2, 0);
			HDMI_EQ_MODE_INDEX =eHDMI_EQ_MODE ;	
			break;
			
		case HDMI_EQ_INDEX_7:
			//HDMI_RegisterWrite(HDMIRX_PHY_EQC0, 1);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQC1, 1);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_0, 1);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_1, 0);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQDC1, 1);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_2, 0);
			HDMI_EQ_MODE_INDEX =eHDMI_EQ_MODE ;	
			break;
			
		case HDMI_EQ_INDEX_8:
			//HDMI_RegisterWrite(HDMIRX_PHY_EQC0, 4);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQC1, 4);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_0, 1);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_1, 0);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQDC1, 1);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_2, 0);
			HDMI_EQ_MODE_INDEX =eHDMI_EQ_MODE ;	
			break;
			
		case HDMI_EQ_INDEX_9:
			//HDMI_RegisterWrite(HDMIRX_PHY_EQC0, 4);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQC1, 4);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_0,0);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_1, 0);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQDC1, 0);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_2, 0);
			HDMI_EQ_MODE_INDEX =eHDMI_EQ_MODE ;	
			break;
			
		case HDMI_EQ_INDEX_10:
			//HDMI_RegisterWrite(HDMIRX_PHY_EQC0, 7);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQC1, 7);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_0, 0);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_1, 0);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQDC1, 0);
			//HDMI_RegisterWrite(HDMIRX_PHY_EQDC0_2, 0);
			HDMI_EQ_MODE_INDEX =eHDMI_EQ_MODE ;	
			break;
			
		/* DEFAULT */
		default:
			printk("[H] mode is not exist\n");
			break;
	}
	HDMI_RegisterWrite(HDMIRX_R_rst_n, 0);
	HDMI_DelayMs(2);
	HDMI_RegisterWrite(HDMIRX_R_rst_n, 1);
}


void HDMI_Set_Demod_Clock_Div(UINT8 FEBDIV, UINT8 PLLGainBit)
{
    if((PLLGainBit <= 31))
    {
        //Set 284[bit:2], 284[bit:3], 263[bit:4] = 0 to Reset Mode
        HDMI_RegisterWrite(HDMIRX_PLL_PWDN_DEMOD, 0x0);
        HDMI_RegisterWrite(HDMIRX_PLL_RESETJ, 0x0);
        HDMI_RegisterWrite(HDMIRX_PLL_PWDN_DEMOD, 0x0);
        HDMI_RegisterWrite(HDMIRX_PLL_RSTN, 0x0);
    	HDMI_DelayUs(1);

        //Set Demod Clock Div
        HDMI_RegisterWrite(HDMIRX_PLL_FEBDIV_7_0_, FEBDIV);
        HDMI_RegisterWrite(HDMIRX_PLL_ICTRL_3_0_, 0x6);
        HDMI_RegisterWrite(HDMIRX_PLL_GB_3_0_, PLLGainBit);
        HDMI_RegisterWrite(HDMIRX_PLL_EN_FDIV, 0x0);

        //Set 284[bit:2] = 1
        HDMI_DelayUs(1);	//PLL Mode need 10 nsec to stable
        HDMI_RegisterWrite(HDMIRX_PLL_PWDN_DEMOD, 0x1);


        //Set 263[bit:4] = 1
        HDMI_DelayUs(1);	//PLL_PWDN_DEMOD need 10 nsec to stable
        HDMI_RegisterWrite(HDMIRX_PLL_RESETJ, 0x1);

        //set 284[bit:3] = 1
        HDMI_DelayUs(1);	//RESETJ need 10 nsec to stable
        HDMI_RegisterWrite(HDMIRX_PLL_PWDN_DEMOD, 0x1);
        HDMI_RegisterWrite(HDMIRX_PLL_RSTN, 0x1);
        HDMI_DelayUs(100);	//CLK_DEMOD need more than 50 usec to stable
    }
    else
    {
        hdmidbg("PLLGainBit value is illegal\n");
    }
}


UINT8 HDMI_Get_HDMI_LDO_PWD(void)
{
	UINT8 ret = 0;
 	//PD0 1/0 : normal / PD (change define from 331)
	ret = (UINT8)HDMI_RegisterRead(HDMIRX_LDO_PWD);
	if(ret==1)
	{
		return HDMI_NORMAL;
	}
	else
	{
		return HDMI_PD;
	}
}

UINT8 HDMI_Get_HDMI_R_SP5_PLL_CTP_PWDJ(void)
{
	UINT8 ret = 0;
	ret = (UINT8)HDMI_RegisterRead(HDMIRX_R_SP5_PLL_CTP_PWDJ);
	return ret;
}

UINT8 HDMI_Get_HDMI_PLL_PWDN_DEMOD(void)
{
	UINT8 ret = 0;
	ret = (UINT8)HDMI_RegisterRead(HDMIRX_PLL_PWDN_DEMOD);
	return ret;
}

UINT8 HDMI_Get_HDMI_COMP_PD(void)
{
	UINT8 ret = 0;
	ret = (UINT8)HDMI_RegisterRead(HDMIRX_COMP_PD);
	return ret;
}

UINT8 HDMI_Get_HDMI_PLL_RESETJ(void)
{
	UINT8 ret = 0;
	ret = (UINT8)HDMI_RegisterRead(HDMIRX_PLL_RESETJ);
	return ret;
}

UINT8 HDMI_Get_HDMI_DEMOD_EN(void)
{
	UINT8 ret = 0;
	ret = (UINT8)HDMI_RegisterRead(HDMIRX_PLL_DEMOD_EN);
	return ret;
}

//------------------------------------------------------------------------------
// Function:    DrvHDMIPortSelectBitsGet
// Description: Reads the HDMI selected port(s)bit-field.  
// Parameters:  None
// Returns:     HDMI selected port(s)bit-field.
//
//------------------------------------------------------------------------------

UINT8 DrvHDMIPortSelectBitsGet(void)
{
	return(HDMI_RegisterRead(HDMIRX_R_hdmi_port_sel));
}


UINT8 HDMI_Get_SPD_INFOFRAME(struct hdmi_spd_infoframe *frame)
{
    hdmi_spd_infoframe_init(frame,
                     (const char*)((HDMIRX_R_SPD_VN_31_0_ & REGISTER_ADDRESS_MASK)+(HDMI_GetRegisterType(HDMIRX_R_SPD_VN_31_0_ & REGISTER_TYPE_MASK))),
                     (const char*)((HDMIRX_R_SPD_PD_31_0_ & REGISTER_ADDRESS_MASK)+(HDMI_GetRegisterType(HDMIRX_R_SPD_PD_31_0_ & REGISTER_TYPE_MASK))),
                     (const char*)((HDMIRX_R_SPD_SDI & REGISTER_ADDRESS_MASK)+(HDMI_GetRegisterType(HDMIRX_R_SPD_SDI & REGISTER_TYPE_MASK))));
    return 0;
}
#ifdef USE_HW_ADAPTIVE_EQ
//parameter 1: HDMIRX_PRE?= PRE0:PRE9, 
//parameter 2: EQC2_2:EQC2_0, value 7~0
//parameter 3: EQC1_2:EQC1_0, value 7~0
//parameter 4: EQC0_2:EQC0_0, value 7~0
//parameter 5: EQDC2_2:EQDC2_0, value 7~0
//parameter 6: EQDC1_2:EQDC1_0, value 7~0
//parameter 7: EQDC0_2:EQDC0_0, value 7~0
#define HDMI_SET_ADAPTIVE_EQ(PRE_INDEX, EQC2,EQC1,EQC0,EQDC2,EQDC1,EQDC0) do{\
        HDMI_RegisterWrite(HDMIRX_ ##PRE_INDEX## _EQC0_2, EQC0&0x4 ? 1:0);\
        HDMI_RegisterWrite(HDMIRX_ ##PRE_INDEX## _EQC0_1, EQC0&0x2 ? 1:0);\
        HDMI_RegisterWrite(HDMIRX_ ##PRE_INDEX## _EQC0_0, EQC0&0x1 ? 1:0);\
        HDMI_RegisterWrite(HDMIRX_ ##PRE_INDEX## _EQC1_2, EQC1&0x4 ? 1:0);\
        HDMI_RegisterWrite(HDMIRX_ ##PRE_INDEX## _EQC1_1, EQC1&0x2 ? 1:0);\
        HDMI_RegisterWrite(HDMIRX_ ##PRE_INDEX## _EQC1_0, EQC1&0x1 ? 1:0);\
        HDMI_RegisterWrite(HDMIRX_ ##PRE_INDEX## _EQC2_2, EQC2&0x4 ? 1:0);\
        HDMI_RegisterWrite(HDMIRX_ ##PRE_INDEX## _EQC2_1, EQC2&0x2 ? 1:0);\
        HDMI_RegisterWrite(HDMIRX_ ##PRE_INDEX## _EQC2_0, EQC2&0x1 ? 1:0);\
        HDMI_RegisterWrite(HDMIRX_ ##PRE_INDEX## _EQDC0_2, EQDC0&0x4 ? 1:0);\
        HDMI_RegisterWrite(HDMIRX_ ##PRE_INDEX## _EQDC0_1, EQDC0&0x2 ? 1:0);\
        HDMI_RegisterWrite(HDMIRX_ ##PRE_INDEX## _EQDC0_0, EQDC0&0x1 ? 1:0);\
        HDMI_RegisterWrite(HDMIRX_ ##PRE_INDEX## _EQDC1_2, EQDC1&0x4 ? 1:0);\
        HDMI_RegisterWrite(HDMIRX_ ##PRE_INDEX## _EQDC1_1, EQDC1&0x2 ? 1:0);\
        HDMI_RegisterWrite(HDMIRX_ ##PRE_INDEX## _EQDC1_0, EQDC1&0x1 ? 1:0);\
        HDMI_RegisterWrite(HDMIRX_ ##PRE_INDEX## _EQDC2_2, EQDC2&0x4 ? 1:0);\
        HDMI_RegisterWrite(HDMIRX_ ##PRE_INDEX## _EQDC2_1, EQDC2&0x2 ? 1:0);\
        HDMI_RegisterWrite(HDMIRX_ ##PRE_INDEX## _EQDC2_0, EQDC2&0x1 ? 1:0);}while(0)
void HDMI_Adaptive_EQ_Init(void)
{
    HDMI_SET_ADAPTIVE_EQ(PRE0,0,0,1,7,2,2);
    HDMI_SET_ADAPTIVE_EQ(PRE1,0,0,2,7,2,2);
    HDMI_SET_ADAPTIVE_EQ(PRE2,0,0,3,7,2,2);
    HDMI_SET_ADAPTIVE_EQ(PRE3,0,0,4,7,2,2);
    HDMI_SET_ADAPTIVE_EQ(PRE4,0,0,7,7,2,2);
    HDMI_SET_ADAPTIVE_EQ(PRE5,0,1,7,7,2,2);
    HDMI_SET_ADAPTIVE_EQ(PRE6,0,2,7,7,2,2);
    HDMI_SET_ADAPTIVE_EQ(PRE7,0,3,7,7,2,2);
    HDMI_SET_ADAPTIVE_EQ(PRE8,0,4,7,7,2,2);
    HDMI_SET_ADAPTIVE_EQ(PRE9,0,7,7,7,2,2);
}
#endif