/**
******************************************************************************
* @file    ms933x_typedef.h
* @author  
* @version V1.0.0
* @date    15-Nov-2014
* @brief   Definitions for typedefs.
*
* Copyright (c) 2009-2014, MacroSilicon Technology Co.,Ltd.
******************************************************************************/
#ifndef __MACROSILICON_MS933X_COMMON_TYPEDEF_H__
#define __MACROSILICON_MS933X_COMMON_TYPEDEF_H__

/*
** Global typedefs.
*/

#ifndef NULL
#define NULL ((void*)0)
#endif

// For ARM platform
#if defined (_PLATFORM_ARM_)
#define  __CODE const
#define  __XDATA
#define  __DATA
#define __IDATA
#define  __NEAR
#define  __IO volatile


typedef _Bool BOOL;

#elif defined (__STD_GCC__)
#define  __CODE const
#define  __XDATA
#define  __DATA
#define __IDATA
#define  __NEAR
#define  __IO volatile


typedef _Bool BOOL;

#elif defined (_PLATFORM_WINDOWS_)
#define  __CODE
#define  __XDATA
#define  __DATA
#define __IDATA
#define  __NEAR
#define  __IO

#elif defined (__KEIL_C__)
#define __CODE code
#define __XDATA xdata
#define __DATA data
#define __IDATA idata
#define __NEAR
#define __IO volatile

//bool bype
typedef bit BOOL;

#elif defined (__CSMC__)
#define __CODE const
#define __XDATA
#define __DATA 
#define __IDATA 
#define __NEAR @near
#define __IO volatile

//bool bype
typedef _Bool BOOL;
#elif defined (_IAR_)
#define __CODE const
#define __XDATA
#define __DATA 
#define __IDATA 
#define __NEAR @near
#define __IO volatile

//bool bype
typedef _Bool BOOL;
#endif // end of compiler platform define 


//unsigned integer type
typedef unsigned char UINT8;
typedef char          CHAR;
typedef unsigned short UINT16;

//signed integer type
typedef signed char INT8;
typedef signed short INT16;

//32bit type
#if defined (_PLATFORM_ARM_) || defined (_PLATFORM_WINDOWS_)
typedef unsigned int UINT32;
typedef signed int INT32;
#else
typedef unsigned long int UINT32;
typedef signed long int INT32;
#endif

#define VOID void

#define FALSE 0
#define TRUE  1

#define DISABLE 0
#define ENABLE  1

#define LOW     0
#define HIGH    1

#define OFF     0
#define ON      1


// Helper macros.
#define _UNUSED_(arg)     ((arg) = (arg))

#ifndef _countof
#define _countof(ARRAY) (sizeof(ARRAY) / sizeof(ARRAY[0]))
#endif

#ifndef max
#define max(a, b)   (((a)>(b))?(a):(b)) 
#endif

#ifndef min
#define min(a, b)   (((a)<(b))?(a):(b))
#endif

#ifndef xabs
#define xabs(a, b)   ((a>b)?(a-b):(b-a))
#endif



/*
* generic mask macro definitions
*/
#define MSRT_BIT0                   (0x01)
#define MSRT_BIT1                   (0x02)
#define MSRT_BIT2                   (0x04)
#define MSRT_BIT3                   (0x08)
#define MSRT_BIT4                   (0x10)
#define MSRT_BIT5                   (0x20)
#define MSRT_BIT6                   (0x40)
#define MSRT_BIT7                   (0x80)
    
#define MSRT_MSB8BITS               MSRT_BIT7
#define MSRT_LSB                    MSRT_BIT0
    
// Bit7 ~ Bit0
#define MSRT_BITS7_6                (0xC0)
#define MSRT_BITS7_5                (0xE0)
#define MSRT_BITS7_4                (0xF0)
#define MSRT_BITS7_3                (0xF8)
#define MSRT_BITS7_2                (0xFC)
#define MSRT_BITS7_1                (0xFE)
#define MSRT_BITS7_0                (0xff)

#define MSRT_BITS6_5                (0x60)
#define MSRT_BITS6_4                (0x70)
#define MSRT_BITS6_2                (0x7c)
#define MSRT_BITS6_1                (0x7e)
#define MSRT_BITS6_0                (0x7f)

#define MSRT_BITS5_4                (0x30)
#define MSRT_BITS5_3                (0x38)
#define MSRT_BITS5_2                (0x3c)
#define MSRT_BITS5_0                (0x3f)

#define MSRT_BITS4_3                (0x18)
#define MSRT_BITS4_2                (0x1c)
#define MSRT_BITS4_1                (0x1e)
#define MSRT_BITS4_0                (0x1f)

#define MSRT_BITS3_2                (0x0C)
#define MSRT_BITS3_1                (0x0E)
#define MSRT_BITS3_0                (0x0F)

#define MSRT_BITS2_1                (0x06)
#define MSRT_BITS2_0                (0x07)

#define MSRT_BITS1_0                (0x03)


// 20121207, for video data type 
typedef struct _T_MS_VIDEO_SIZE_
{
    UINT16 u16_h;
    UINT16 u16_v;
} VIDEOSIZE_T;

typedef struct _T_MS933X_VIDEO_TIMING_
{
    UINT8           u8_polarity;
    UINT16          u16_htotal;
    UINT16          u16_vtotal;
    UINT16          u16_hactive;
    UINT16          u16_vactive;
    UINT16          u16_pixclk;     /*10000hz*/
    UINT16          u16_vfreq;      /*0.01hz*/
    UINT16          u16_hoffset;    /* h sync start to h active*/
    UINT16          u16_voffset;    /* v sync start to v active*/
    UINT16          u16_hsyncwidth;
    UINT16          u16_vsyncwidth;
} VIDEOTIMING_T;


typedef struct _T_WIN_BORDER_
{
    INT16 top;
    INT16 bottom;
    INT16 left;
    INT16 right;
} WINBORDER_T;


//
//HDMI video
typedef enum _E_HDMI_VIDEO_CLK_REPEAT_
{
    HDMI_X1CLK      = 0x00,
    HDMI_X2CLK      = 0x01,
    HDMI_X3CLK      = 0x02,
    HDMI_X4CLK      = 0x03,
    HDMI_X5CLK      = 0x04,
    HDMI_X6CLK      = 0x05,
    HDMI_X7CLK      = 0x06,
    HDMI_X8CLK      = 0x07,
    HDMI_X9CLK      = 0x08,
    HDMI_X10CLK     = 0x09
}HDMI_CLK_RPT_E;

//u8_aspect_ratio, bit3
#define HDMI_ACTIVE_ASPECT_RATIO_PRESENT    (0x08) //active Format(R0...R3) information valid

//u8_aspect_ratio, bits1_0
typedef enum _E_HDMI_PIC_ASPECT_RATIO_
{
    HDMI_PIC_ASPECT_RATIO_UNKONWN   = 0x00,
    HDMI_4X3                        = 0x01,
    HDMI_16X9                       = 0x02,
    HDMI_PIC_ASPECT_RATIO_FUTURE    = 0x03
}HDMI_ASPECT_RATIO_E;

//u8_aspect_ratio, bits7_4, active format aspect ratio R3 R2 R1 R0
typedef enum _E_HDMI_ACTIVE_FORMAT_ASPECT_RATIO_
{
    HDMI_ACT_ASP_SAME_AS_PIC = 0x80,
    HDMI_ACT_ASP_4X3_C       = 0x90,
    HDMI_ACT_ASP_16X9_C      = 0xA0,
    HDMI_PIC_ACT_ASP_14X9_C  = 0xB0
    //others unknown
}HDMI_ACTIVE_FORMAT_ASPECT_RATIO_E;

typedef enum _E_HDMI_VIDEO_SCAN_INFO_
{
    HDMI_UNKNOWN_SCAN  = 0x00,    //unknown scan info
    HDMI_OVERSCAN      = 0x01,    //television type
    HDMI_UNDERSCAN     = 0x02     //computer type
}HDMI_SCAN_INFO_E;

typedef enum _E_HDMI_COLOR_SPACE_
{
    HDMI_RGB        = 0x00,
    HDMI_YCBCR422   = 0x01,
    HDMI_YCBCR444   = 0x02,
    HDMI_YUV420     = 0x03
}HDMI_CS_E;

typedef enum _E_HDMI_COLOR_DEPTH_
{
    HDMI_COLOR_DEPTH_8BIT    = 0x00,
    HDMI_COLOR_DEPTH_10BIT   = 0x01,
    HDMI_COLOR_DEPTH_12BIT   = 0x02,
    HDMI_COLOR_DEPTH_16BIT   = 0x03
}HDMI_COLOR_DEPTH_E;

typedef enum _E_HDMI_COLORIMETRY_
{
    HDMI_COLORIMETRY_UNKNOWN                = 0x00,
    //
    HDMI_COLORIMETRY_601                    = 0x01, //IT601 = 480i/576i/480p/576p or VESA timing
    HDMI_COLORIMETRY_709                    = 0x02, //YCbCr

    //COLORIMETRY extented:
    HDMI_COLORIMETRY_XVYCC601               = 0x03, //xvYCC601
    HDMI_COLORIMETRY_XVYCC709               = 0x04, //xvYCC709
    HDMI_COLORIMETRY_SYCC601                = 0x05, //sYCC601
    HDMI_COLORIMETRY_ADOBEYCC601            = 0x06, //opYCC
    HDMI_COLORIMETRY_ADOBERGB               = 0x07, //opRGB
    HDMI_COLORIMETRY_ITU_R_BT2020YcCbcCrc   = 0x08, //BT2020_cYCC
    HDMI_COLORIMETRY_ITU_R_BT2020RGBORYCbCr = 0x09, //BT2020_YCC or BT2020_RGB
    HDMI_COLORIMETRY_RESERVED               = 0x0A
}HDMI_COLORIMETRY_E;

//u8_quant_range, bits1_0
typedef enum _E_HDMI_RRG_QUANT_RANGE_
{
    HDMI_RGB_QUANT_DEFAULT       = 0x00, 
    HDMI_RGB_QUANT_LIMITED       = 0x01, 
    HDMI_RGB_QUANT_FULL          = 0x02, 
    HDMI_RGB_QUANT_RESERVED      = 0x03 
}HDMI_RGB_QUANT_RANGE_E;

//u8_quant_range, bits5_4
typedef enum _E_HDMI_YCC_QUANT_RANGE_
{
    HDMI_YCC_QUANT_LIMITED       = 0x00, 
    HDMI_YCC_QUANT_FULL          = 0x10, 
    HDMI_YCC_QUANT_RESERVED      = 0x20, 
    HDMI_YCC_QUANT_RESERVED1     = 0x30 
}HDMI_YCC_QUANT_RANGE_E;

//u8_it_content, bits3_0
typedef enum _E_HDMI_IT_CONTENT_
{
    HDMI_IT_CONTENT_INVALID      = 0x00,
    //
    HDMI_IT_CONTENT_GRAPHICS     = 0x01, //Graphics
    HDMI_IT_CONTENT_PHOTO        = 0x02, //Photo
    HDMI_IT_CONTENT_CINEMA       = 0x03, //Cinema
    HDMI_IT_CONTENT_GAME         = 0x04  //Game
}HDMI_IT_CONTENT_E;

//HDMI vendor specific
typedef enum _E_HDMI_VIDEO_FORMAT_
{
    HDMI_NO_ADD_FORMAT,
    HDMI_4Kx2K_FORMAT,
    HDMI_3D_FORMAT
}HDMI_VIDEO_FORMAT_E;

typedef enum _E_HDMI_4Kx2K_VIC_
{
    HDMI_4Kx2K_30HZ = 0x01,
    HDMI_4Kx2K_25HZ,
    HDMI_4Kx2K_24HZ,
    HDMI_4Kx2K_24HZ_SMPTE
}HDMI_4Kx2K_VIC_E;

//use u8_4Kx2K_vic bits7_4 store u8_3D_structure
typedef enum _E_HDMI_3D_STRUCTURE_
{
    HDMI_FRAME_PACKING      = 0x00,
    HDMI_FIELD_ALTERNATIVE  = 0x10,
    HDMI_LINE_ALTERNATIVE   = 0x20,
    HDMI_SIDE_BY_SIDE_FULL  = 0x30,
    HDMI_L_DEPTH            = 0x40,
    HDMI_L_DEPTH_GRAPHICS   = 0x50,
    HDMI_SIDE_BY_SIDE_HALF  = 0x80
}HDMI_3D_STRUCTURE_E;

//u8_3D_ext_data, bits7_4
typedef enum _E_HDMI_3D_EXT_DATA_
{
    HDMI_HORIZONTAL_O_O    = 0x00,
    HDMI_HORIZONTAL_O_E    = 0x10,
    HDMI_HORIZONTAL_E_O    = 0x20,
    HDMI_HORIZONTAL_E_E    = 0x30,

    HDMI_QUINCUNX_O_O      = 0x40,
    HDMI_QUINCUNX_O_E      = 0x50,
    HDMI_QUINCUNX_E_O      = 0x60,
    HDMI_QUINCUNX_E_E      = 0x70 
}HDMI_3D_EXT_DATA_E;


//u8_audio_mode BIT6
#define HDMI_AUDIO_SPDIF_PATH_ENABLE        (0x40)

//HDMI audio, u8_audio_mode: BITS5_4
typedef enum _E_HDMI_AUDIO_MODE_
{
    HDMI_AUD_MODE_AUDIO_SAMPLE  = 0x00,
    HDMI_AUD_MODE_HBR           = 0x10, //unsupport
    HDMI_AUD_MODE_DSD           = 0x20,
    HDMI_AUD_MODE_DST           = 0x30  //unsupport
}HDMI_AUDIO_MODE_E;

//audio coding type from audio inforframe, u8_audio_mode BITS3_0
typedef enum _E_HDMI_AUDIO_CODING_TYPE_
{
    HDMI_AUD_CT_REFER_HEADER  = 0x00, //audio inforframe audio type refer to audio packet header
    HDMI_AUD_CT_PCM           = 0x01,
    HDMI_AUD_CT_AC_3          = 0x02,
    HDMI_AUD_CT_MPEG1         = 0x03,
    HDMI_AUD_CT_MP3           = 0x04,
    HDMI_AUD_CT_MPEG2         = 0x05,
    HDMI_AUD_CT_AAC           = 0x06,
    HDMI_AUD_CT_DTS           = 0x07,
    HDMI_AUD_CT_ATRAC         = 0x08,
    HDMI_AUD_CT_OBA           = 0x09,
    HDMI_AUD_CT_DOLBY_PLUS    = 0x0A,
    HDMI_AUD_CT_DTS_HD        = 0x0B,
    HDMI_AUD_CT_MAT           = 0x0C,
    HDMI_AUD_CT_DST           = 0x0D,
    HDMI_AUD_CT_WMA           = 0x0E,
    HDMI_AUD_CT_WMA_PRO       = 0x0F
}HDMI_AUDIO_CT_E;

//if audio infoframe audio rate no refer to audio packet header, u8_audio_rate BIT7 = 1
#define HDMI_AUD_RATE_NO_REFER_HEADER       (0x80)

//u8_audio_rate, BITS6_4
typedef enum _E_HDMI_AUDIO_RATE_
{
    HDMI_AUD_RATE_44K1  = 0x20,
    HDMI_AUD_RATE_48K   = 0x30,
    HDMI_AUD_RATE_32K   = 0x10,
    HDMI_AUD_RATE_88K2  = 0x40,
    HDMI_AUD_RATE_96K   = 0x50,
    HDMI_AUD_RATE_176K4 = 0x60,
    HDMI_AUD_RATE_192K  = 0x70
}HDMI_AUDIO_RATE_E;

//u8_audio_rate, BITS3_0
//refer to SPEC "IEC-60958-3-Digital-Audio"
typedef enum _E_HDMI_AUDIO_HEADER_RATE_
{
    HDMI_AUD_HEADER_RATE_44K1  = 0x00,
    HDMI_AUD_HEADER_RATE_48K   = 0x02,
    HDMI_AUD_HEADER_RATE_32K   = 0x03,
    HDMI_AUD_HEADER_RATE_88K2  = 0x08,
    HDMI_AUD_HEADER_RATE_96K   = 0x0A,
    HDMI_AUD_HEADER_RATE_176K4 = 0x0C,
    HDMI_AUD_HEADER_RATE_192K  = 0x0E,
    //
    HDMI_AUD_HEADER_RATE_22K01 = 0x04,  //
    HDMI_AUD_HEADER_RATE_24K   = 0x06,  //
    HDMI_AUD_HEADER_RATE_768K  = 0x09   //
}HDMI_AUDIO_HEADER_RATE_E;

//if audio infoframe audio bits no refer to audio packet header, u8_audio_bits BIT7 = 1
#define HDMI_AUD_LENGTH_NO_REFER_HEADER     (0x80)

//u8_audio_bits, BITS5_4
typedef enum _E_HDMI_AUDIO_LENGTH_
{
    HDMI_AUD_LENGTH_16BITS    = 0x10,
    HDMI_AUD_LENGTH_20BITS    = 0x20,
    HDMI_AUD_LENGTH_24BITS    = 0x30
}HDMI_AUDIO_LENGTH_E;

//u8_audio_bits, BITS3_0
//refer to SPEC "IEC-60958-3-Digital-Audio"
typedef enum _E_HDMI_AUDIO_HEADER_LENGTH_
{
    HDMI_AUD_HEADER0_LENGTH_16BITS    = 0x02,
    HDMI_AUD_HEADER0_LENGTH_18BITS    = 0x04,
    HDMI_AUD_HEADER0_LENGTH_19BITS    = 0x08,
    HDMI_AUD_HEADER0_LENGTH_20BITS    = 0x0A,
    HDMI_AUD_HEADER0_LENGTH_17BITS    = 0x0C,
    //
    HDMI_AUD_HEADER1_LENGTH_20BITS    = 0x03,
    HDMI_AUD_HEADER1_LENGTH_22BITS    = 0x05,
    HDMI_AUD_HEADER1_LENGTH_23BITS    = 0x09,
    HDMI_AUD_HEADER1_LENGTH_24BITS    = 0x0B,
    HDMI_AUD_HEADER1_LENGTH_21BITS    = 0x0D
}HDMI_AUDIO_HEADER_LENGTH_E;

//if audio inforframe audio channel refer to audio packet header, u8_audio_channels BIT7 = 1
#define HDMI_AUDIO_CHN_REFER_HEADER         (0x80)

//if audio channel layout1, u8_audio_channels BIT6 = 1
#define HDMI_AUDIO_CHN_LAYOUT1_ENABLE       (0x40)

//u8_audio_channels, BITS3_0
typedef enum _E_HDMI_AUDIO_CHANNEL_
{
    HDMI_AUD_2CH    = 0x01,
    HDMI_AUD_3CH    = 0x02,
    HDMI_AUD_4CH    = 0x03,
    HDMI_AUD_5CH    = 0x04,
    HDMI_AUD_6CH    = 0x05,
    HDMI_AUD_7CH    = 0x06,
    HDMI_AUD_8CH    = 0x07
}HDMI_AUDIO_CHN_E;



typedef struct _T_HDMI_CONFIG_PARA_
{   
    UINT8  u8_hdmi_flag;          // FALSE = dvi out;  TRUE = hdmi out
    UINT8  u8_vic;                // reference to CEA-861 VIC
    UINT16 u16_video_clk;         // TMDS video clk, uint 10000Hz
    UINT8  u8_clk_rpt;            // enum refer to HDMI_CLK_RPT_E. X2CLK = 480i/576i, others = X1CLK
    UINT8  u8_scan_info;          // enum refer to HDMI_SCAN_INFO_E
    
    UINT8  u8_aspect_ratio;       // bits1_0 enum refer to HDMI_ASPECT_RATIO_E 
                                  // bit3(HDMI_ACTIVE_ASPECT_RATIO_PRESENT) 
                                  // bits7_4 enum refer to HDMI_ACTIVE_FORMAT_ASPECT_RATIO_E
                                  
    UINT8  u8_color_space;        // enum refer to HDMI_CS_E
    UINT8  u8_color_depth;        // enum refer to HDMI_COLOR_DEPTH_E
    UINT8  u8_colorimetry;        // enum refer to HDMI_COLORIMETRY_E. IT601 = 480i/576i/480p/576p, ohters = IT709

    UINT8  u8_quant_range;        // bits1_0 enum refer to HDMI_RGB_QUANT_RANGE_E
                                  // bits5_4 enum refer to HDMI_YCC_QUANT_RANGE_E

    UINT8  u8_it_content;         // bits3_0 enum refer to HDMI_IT_CONTENT_E

    //
    UINT8  u8_video_format;       // enum refer to HDMI_VIDEO_FORMAT_E
    UINT8  u8_4Kx2K_vic;          // enum refer to HDMI1.4 extented resolution transmission
    UINT8  u8_3D_structure;       // enum refer to HDMI_3D_EXT_DATA_E

    //
    UINT8  u8_audio_mode;         // BITS5_4 enum refer to HDMI_AUDIO_MODE_E
                                  // BITS3_0 enum refer to HDMI_AUDIO_CT_E
                                  // BIT6 reserve for test. enum refer to HDMI_AUDIO_SPDIF_PATH_ENABLE
                                  
    UINT8  u8_audio_rate;         // BITS6_4 enum refer to HDMI_AUDIO_RATE_E 
                                  // BITS3_0 enum refer to HDMI_AUDIO_HEADER_RATE_E
                                  // BIT7 is HDMI_AUD_RATE_NO_REFER_HEADER

    UINT8  u8_audio_bits;         // BITS5_4 enum refer to HDMI_AUDIO_LENGTH_E
                                  // BITS3_0 enum refer to HDMI_AUDIO_HEADER_LENGTH_E
                                  // BIT7 is HDMI_AUD_LENGTH_NO_REFER_HEADER
                                     
    UINT8  u8_audio_channels;     // BITS3_0 enum refer to HDMI_AUDIO_CHN_E 
                                  // BIT7 is HDMI_AUDIO_CHN_REFER_HEADER
                                  // BIT6 is HDMI_AUDIO_CHN_LAYOUT1_ENABLE
    UINT8  u8_audio_speaker_locations;  // 0~255, refer to CEA-861 audio infoframe, BYTE4
}HDMI_CONFIG_T;



//HDMI RX module define
typedef enum
{
    HDMI_RX_CH0,
    HDMI_RX_CH1,
    HDMI_RX_CH2
}e_RxChannel;

typedef enum
{
    OVERSAMPLE_DESIGNED,
    OVERSAMPLE_NETLIST,
    PI
}e_RxPhy;

typedef enum
{
    AUTO_MODE,
    MANUAL_MODE
}e_RxPhyMode;

typedef struct
{
    UINT8  u8OffsetP;
    UINT8  u8OffsetN;
}OFFSET_T;

//ms933xdrv_hdmi_rx_audio_config
//u8_audio_clk_mode,bit7. if set to 1, pad_i2s_out mclk base is 256fs.
//no suuport when RX_AUDIO_DLL_MODE case.
#define RX_AUDIO_MCLK_BASE_256FS_ENABLE     (0x80) 

//u8_audio_clk_mode, bit3_0
typedef enum
{
    RX_AUDIO_DLL_MODE          = 0x00, //user use
    RX_AUDIO_DLL_TO_PLL_MODE   = 0x01, //user use
    RX_AUDIO_DLL_TO_2XPLL_MODE = 0x02,
    RX_AUDIO_PLL_MODE          = 0x03,
    RX_AUDIO_PLL_FREERUN_MODE  = 0x04
}e_RxAudioClkMode;

typedef enum
{
    MDT_ProgrVNegHNeg = 0x01,
    MDT_ProgrVNegHPos = 0x03,
    MDT_ProgrVPosHNeg = 0x05,
    MDT_ProgrVPosHPos = 0x07,

    MDT_InterVNegHNeg = 0x00,
    MDT_InterVNegHPos = 0x02,
    MDT_InterVPosHNeg = 0x04,
    MDT_InterVPosHPos = 0x06
}e_RxMdtPol;

typedef struct TERRORCOUNTER
{
//    BOOL b;
    UINT16 u16Count;
}ERRORCOUNTER;

//hdmi_rx_reset_ctrl
#define HDMI_RX_CTRL_MAIN  (0x00001UL)
#define HDMI_RX_CTRL_MODET (0x00002UL)
#define HDMI_RX_CTRL_HDMI  (0x00004UL)
#define HDMI_RX_CTRL_BUS   (0x00008UL)
#define HDMI_RX_CTRL_AUD   (0x00010UL)
#define HDMI_RX_CTRL_PDEC  (0x00020UL) //20180607, PACKET DECODER reset
#define HDMI_RX_CTRL_PIXEL (0x00040UL)
#define HDMI_RX_CTRL_VID   (0x00080UL) //hdcp reset
#define HDMI_RX_CTRL_HDCP  (0x00100UL) //video reset
#define HDMI_RX_CTRL_TMDS  (0x10000UL)

typedef enum _E_MDT_INTRRUPT_STATUS_
{
    MDT_HS_ACT_ISTS         = 0x001, //used
    MDT_VS_ACT_ISTS         = 0x002, //
    MDT_DE_ACTIVITY_ISTS    = 0x004, //used
    MDT_ILACE_ISTS          = 0x008, //
    MDT_HTOT32_CLK_ISTS     = 0x010,
    MDT_HS_CLK_ISTS         = 0x020, //20220512, unused
    MDT_HACT_PIX_ISTS       = 0x040, //used
    MDT_VTOT_CLK_ISTS       = 0x080, 
    MDT_VS_CLK_ISTS         = 0x100,
    MDT_VACT_LIN_ISTS       = 0x200,  //20220512, unused
    MDT_VTOT_LIN_ISTS       = 0x400,  //20220512, unused
    MDT_VOFS_LIN_ISTS       = 0x800,  //20220512, unused
    MDT_STB_ISTS            = 0x1000, 
    MDT_USTB_ISTS           = 0x2000  //used

    //
    //MDT_ALL_ISTS            = 0xffff  //20220512, unused
}MDTISTS_E;

#define MDT_USED_ISTS      (0x2045)

typedef enum _E_AUDIO_FIFO_STATUS_
{
    AFIF_TH_MIN_STS         = 0x001,
    AFIF_TH_MAX_STS         = 0x002,
    AFIF_THS_PASS_STS       = 0x004,
    AFIF_UNDERFL_STS        = 0x008,
    AFIF_OVERFL_STS         = 0x010
}AUDIO_FIFO_STATUS_E;

//hdmi_rx_packet_ists
#define PD_FIFO_TH_MIN_PASS_ISTS   (1UL << 0)
#define PD_FIFO_TH_MAX_PASS_ISTS   (1UL << 1)
#define PD_FIFO_TH_START_PASS_ISTS (1UL << 2)
#define PD_FIFO_UNDERFL_ISTS       (1UL << 3)
#define PD_FIFO_OVERFL_ISTS        (1UL << 4)
#define PD_FIFO_NEW_ENTRY_ISTS     (1UL << 8)
#define NTSCVBI_RCV_ISTS           (1UL << 11)
#define NTSCVBI_CKS_CHG_ISTS       (1UL << 12)
#define AMP_CHG_ISTS               (1UL << 13)
#define AMP_RCV_ISTS               (1UL << 14)
#define VSI_RCV_ISTS               (1UL << 15)
#define GCP_RCV_ISTS               (1UL << 16)
#define ACR_RCV_ISTS               (1UL << 17)
#define AVI_RCV_ISTS               (1UL << 18)
#define AIF_RCV_ISTS               (1UL << 19)
#define GMD_RCV_ISTS               (1UL << 20)
#define GCP_AV_MUTE_CHG_ISTS       (1UL << 21)
#define ACR_CTS_CHG_ISTS           (1UL << 22)
#define ACR_N_CHG_ISTS             (1UL << 23)
#define AVI_CKS_CHG_ISTS           (1UL << 24)
#define AIF_CKS_CHG_ISTS           (1UL << 25)
#define GMD_CKS_CHG_ISTS           (1UL << 26)
#define VSI_CKS_CHG_ISTS           (1UL << 27)
#define DVIDET_ISTS                (1UL << 28)
#define AUD_TYPE_CHG_ISTS          (1UL << 29)
#define DRM_RCV_ISTS               (1UL << 30)
#define DRM_CKS_CHG_ISTS           (1UL << 31)
//#define PDEC_ALL_ISTS              (0xffffffffUL)
#define PEDC_USED_ISTS             (0xfffffE00UL) //mask never used int bit.

//hdmi_rx_hdmi_ists
#define STATE_REACHED_ISTS              (1UL << 0)
#define ACT_CHANGE_ISTS                 (1UL << 1)
#define RESCAL_DONE_ISTS                (1UL << 2)
#define OFFSCAL_DONE_ISTS               (1UL << 3)
#define EQGAIN_DONE_ISTS                (1UL << 4)
#define PLL_LCK_CHG_ISTS                (1UL << 5)
#define CLK_CHANGE_ISTS                 (1UL << 6)
#define RES_OVERLOAD_ISTS               (1UL << 7)
#define HS_POL_ADJ_ISTS                 (1UL << 8)
#define VS_POL_ADJ_ISTS                 (1UL << 9)
#define CTL0_CHANGE_ISTS                (1UL << 10)
#define CTL1_CHANGE_ISTS                (1UL << 11)
#define CTL2_CHANGE_ISTS                (1UL << 12)
#define CTL3_CHANGE_ISTS                (1UL << 13)
#define DCM_GCP_ZERO_FIELDS_PASS_ISTS   (1UL << 14)
#define DCM_PH_DIFF_CNT_OVERFL_ISTS     (1UL << 15)
#define DCM_CURRENT_MODE_CHG_ISTS       (1UL << 16)
#define SCDCCFGCHANGE_ISTS              (1UL << 17)
#define SCDCSCSTATUSCHANGE_ISTS         (1UL << 18)
#define SCDCTMDSCFGCHANGE_ISTS          (1UL << 19)
#define CEAVID_FULL_ISTS                (1UL << 20)
#define CEAVID_EMPTY_ISTS               (1UL << 21)
#define CDSENSE_CHG_ISTS                (1UL << 22)
#define DESER_MISAL_ISTS                (1UL << 23)
#define PLL_CLOCK_GATED_ISTS            (1UL << 24)
#define AKSV_RCV_ISTS                   (1UL << 25)
#define VSYNC_ACT_EDGE_ISTS             (1UL << 26)
#define VS_THR_REACHED_ISTS             (1UL << 27)
#define I2CMPDONE_ISTS                  (1UL << 28)
#define I2CMPNACK_ISTS                  (1UL << 29)
#define I2CMP_ARBLOST_ISTS              (1UL << 30)
#define HDMI_ALL_ISTS                   (0xffffffffUL)



//HDMI TX module define

//HDMI TX channel
typedef enum _E_HDMI_TX_CHANNEL_
{
    HDMI_TX_CHN0      = 0x00,
    HDMI_TX_CHN1      = 0x01,
    HDMI_TX_CHN2      = 0x02,
    HDMI_TX_CHN3      = 0x03
}HDMI_CHANNEL_E;

typedef struct _T_HDMI_HDCP_RI_
{   
    UINT8 TX_Ri0;
    UINT8 TX_Ri1;
    UINT8 RX_Ri0;
    UINT8 RX_Ri1;
}HDMI_HDCP_RI;

#define HDCP_KSV_BYTE_SIZE                 (5)

#define HDCP_RPT_RPT_DEV_COUNT_MAX         (0x7F)
#define HDCP_RPT_RPT_DEV_DEPTH_MAX         (0x07)

#define MS933X_HDCP_RPT_KSV_FIFO_BYTE_MAX  (128)
#define MS933X_HDCP_RPT_COUNT_MAX          (24) //24*5=120byte


#define HDCP_REPEATER_FLAG_BIT_MASK        (0x40)
#define HDCP_KSV_FIFO_READY_BIT_MASK       (0x20)
#define HDCP_MAX_DEVS_EXCEEDED_BIT_MASK    (0x80)
#define HDCP_MAX_CASCADE_EXCEEDED_BIT_MASK (0x08)

//HDMI EDID
typedef struct _T_HDMI_EDID_FLAG_
{   
    UINT8    u8_hdmi_sink;              //1 = HDMI sink, 0 = dvi
    UINT8    u8_color_space;            //color space support flag, flag 1 valid. BIT5: YCBCR444 flag; BIT4: YCBCR422 flag.(RGB must be support)
    //
    UINT8    u8_edid_total_blocks;      //block numbers, 128bytes in one block
    UINT16   u16_preferred_pixel_clk;   //EDID Preferred pixel clock rate, u16_preferred_pixel_clk * 10000Hz, ERROR code is 0xFFFF
    UINT32   u32_preferred_timing;      //EDID Preferred Timing (Hact*Vact)
    UINT8    u8_max_tmds_clk;           //HDMI VSDB max tmds clock, u8_max_tmds_clk * 5 Mhz
    UINT32   u32_max_video_block_timing;//EDID max video block timing (Hact*Vact)
    UINT8    u8_hdmi_2_0_flag;          //1 = HDMI 2.0
}HDMI_EDID_FLAG_T;

//
typedef struct _T_HDMI_TX_DRIVE_
{   
    UINT8 u8_tx_phy_reg0x20; //[6]:   RG_HDMITX_R200_EN; 
    UINT8 u8_tx_phy_reg0x23; //[0]:   RG_POST_PRE0_EN;     [1]: RG_POST_PRE1_EN;   [2]: RG_POST_PRE2_EN;   [4]:RG_TX_IDRV_6M_EN;
    UINT8 u8_tx_phy_reg0x24; //[2:0]: RG_MAIN_PRE0;      [6:4]: RG_MAIN_PRE1;
    UINT8 u8_tx_phy_reg0x25; //[2:0]: RG_MAIN_PRE2;      [6:4]: RG_MAIN_PREC;
    UINT8 u8_tx_phy_reg0x26; //[3:0]: RG_MAIN_PO0;       [7:4]: RG_MAIN_PO1;
    UINT8 u8_tx_phy_reg0x27; //[3:0]: RG_MAIN_PO2;       [7:4]: RG_MAIN_POC;
    UINT8 u8_tx_phy_reg0x28; //[3:0]: RG_POST_PO0;       [7:4]: RG_POST_PO1;
    UINT8 u8_tx_phy_reg0x29; //[3:0]: RG_POST_PO2
}HDMI_TX_DRIVE_T;


#endif  // __MACROSILICON_MS933X_COMMON_TYPEDEF_H__
