PIOC_SFR.h 15 KB

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  1. /* Define for PIOC */
  2. /* Website: http://wch.cn */
  3. /* Email: tech@wch.cn */
  4. /* Author: W.ch 2022.08 */
  5. /* V1.0 SpecialFunctionRegister */
  6. // __PIOC_SFR_H__
  7. #ifndef __PIOC_SFR_H__
  8. #define __PIOC_SFR_H__
  9. #ifdef __cplusplus
  10. extern "C" {
  11. #endif
  12. // Register Bit Attribute / Bit Access Type
  13. // RO: Read Only (internal change)
  14. // RW: Read / Write
  15. // Attribute: master/PIOC
  16. /* Register name rule:
  17. R32_* for 32 bits register (UINT32,ULONG)
  18. R16_* for 16 bits register (UINT16,USHORT)
  19. R8_* for 8 bits register (UINT8,UCHAR)
  20. RB_* for bit or bit mask of 8 bit register */
  21. /* ********************************************************************************************************************* */
  22. #define PIOC_SRAM_BASE (SRAM_BASE+0x4000) // PIOC code RAM base address
  23. #define PIOC_SFR_BASE PIOC_BASE // PIOC SFR base address
  24. #define R32_PIOC_SFR (*((volatile unsigned long *)(PIOC_SFR_BASE+0x04))) // RO/RW, PIOC SFR
  25. #define R8_INDIR_ADDR (*((volatile unsigned char *)(PIOC_SFR_BASE+0x04))) // RO/RW, PIOC indirect address
  26. #define R8_TMR0_COUNT (*((volatile unsigned char *)(PIOC_SFR_BASE+0x05))) // RO/RW, PIOC timer count
  27. #define R8_TMR0_CTRL (*((volatile unsigned char *)(PIOC_SFR_BASE+0x06))) // RO/RW, PIOC timer control and GP bit
  28. #define RB_EN_LEVEL1 0x80 // RO/RW, enable IO1 level change to wakeup & action interrupt flag
  29. #define RB_EN_LEVEL0 0x40 // RO/RW, enable IO0 level change to wakeup & action interrupt flag
  30. #define RB_GP_BIT_Y 0x20 // RO/RW, general-purpose bit 1, reset by power on, no effect if system reset or RB_MST_RESET reset
  31. #define RB_GP_BIT_X 0x10 // RO/RW, general-purpose bit 0, reset by power on, no effect if system reset or RB_MST_RESET reset
  32. #define RB_TMR0_MODE 0x08 // RO/RW, timer mode: 0-timer, 1-PWM
  33. #define RB_TMR0_FREQ2 0x04 // RO/RW, timer clock frequency selection 2
  34. #define RB_TMR0_FREQ1 0x02 // RO/RW, timer clock frequency selection 1
  35. #define RB_TMR0_FREQ0 0x01 // RO/RW, timer clock frequency selection 0
  36. #define R8_TMR0_INIT (*((volatile unsigned char *)(PIOC_SFR_BASE+0x07))) // RO/RW, PIOC timer initial value
  37. #define R32_PORT_CFG (*((volatile unsigned long *)(PIOC_SFR_BASE+0x08))) // RO/RW, port status and config
  38. #define R8_BIT_CYCLE (*((volatile unsigned char *)(PIOC_SFR_BASE+0x08))) // RO/RW, encode bit cycle
  39. #define RB_BIT_TX_O0 0x80 // RO/RW, bit data for IO0 port encode output
  40. #define RB_BIT_CYCLE 0x7F // RO/RW, IO0 port bit data cycle -1
  41. #define R8_INDIR_ADDR2 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x09))) // RO/RW, PIOC indirect address 2
  42. #define R8_PORT_DIR (*((volatile unsigned char *)(PIOC_SFR_BASE+0x0A))) // RO/RW, IO port direction and mode
  43. //#define RB_PORT_MOD3 0x80 // RO/RW, IO port mode 3
  44. //#define RB_PORT_MOD2 0x40 // RO/RW, IO port mode 2
  45. //#define RB_PORT_MOD1 0x20 // RO/RW, IO port mode 1
  46. //#define RB_PORT_MOD0 0x10 // RO/RW, IO port mode 0
  47. //#define RB_PORT_PU1 0x08 // RO/RW, IO1 port pullup enable
  48. //#define RB_PORT_PU0 0x04 // RO/RW, IO0 port pullup enable
  49. #define RB_PORT_DIR1 0x02 // RO/RW, IO1 port direction
  50. #define RB_PORT_DIR0 0x01 // RO/RW, IO0 port direction
  51. #define R8_PORT_IO (*((volatile unsigned char *)(PIOC_SFR_BASE+0x0B))) // RO/RW, IO port input and output
  52. #define RB_PORT_IN_XOR 0x80 // RO/RO, IO0 XOR IO1 port input
  53. #define RB_BIT_RX_I0 0x40 // RO/RO, decoced bit data for IO0 port received
  54. #define RB_PORT_IN1 0x20 // RO/RO, IO1 port input
  55. #define RB_PORT_IN0 0x10 // RO/RO, IO0 port input
  56. #define RB_PORT_XOR1 0x08 // RO/RO, IO1 port output XOR input
  57. #define RB_PORT_XOR0 0x04 // RO/RO, IO0 port output XOR input
  58. #define RB_PORT_OUT1 0x02 // RO/RW, IO1 port output
  59. #define RB_PORT_OUT0 0x01 // RO/RW, IO0 port output
  60. #define R32_DATA_CTRL (*((volatile unsigned long *)(PIOC_SFR_BASE+0x1C))) // RW/RW, data control
  61. #define R8_SYS_CFG (*((volatile unsigned char *)(PIOC_SFR_BASE+0x1C))) // RW/RW, port config
  62. #define RB_INT_REQ 0x80 // RO/RW, PIOC interrupt request action, set 1/0 by PIOC, clear 0 by master write R8_CTRL_RD (no effect)
  63. #define RB_DATA_SW_MR 0x40 // RO/RO, R8_CTRL_RD wait for read status, set 1 by PIOC write R8_CTRL_RD, clear 0 by master read R8_CTRL_RD
  64. #define RB_DATA_MW_SR 0x20 // RO/RO, R8_CTRL_WR wait for read status, set 1 by master write R8_CTRL_WR, clear 0 by PIOC read R8_CTRL_WR
  65. #define RB_MST_CFG_B4 0x10 // RW/RO, config inform bit, default 0
  66. #define RB_MST_IO_EN1 0x08 // RW/RO, IO1 switch enable, default 0
  67. #define RB_MST_IO_EN0 0x04 // RW/RO, IO0 switch enable, default 0
  68. #define RB_MST_RESET 0x02 // RW/RO, force PIOC reset, high action, default 0
  69. #define RB_MST_CLK_GATE 0x01 // RW/RO, PIOC global clock enable, high action, default 0
  70. #define R8_CTRL_RD (*((volatile unsigned char *)(PIOC_SFR_BASE+0x1D))) // RO/RW, data for master read only and PIOC write only
  71. #define R8_CTRL_WR (*((volatile unsigned char *)(PIOC_SFR_BASE+0x1E))) // RW/RO, data for master write only and PIOC read only
  72. #define R8_DATA_EXCH (*((volatile unsigned char *)(PIOC_SFR_BASE+0x1F))) // RW/RW, data exchange
  73. #define R32_DATA_REG0_3 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x20))) // RW/RW, data buffer 0~3
  74. #define R8_DATA_REG0 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x20))) // RW/RW, data buffer 0
  75. #define R8_DATA_REG1 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x21))) // RW/RW, data buffer 1
  76. #define R8_DATA_REG2 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x22))) // RW/RW, data buffer 2
  77. #define R8_DATA_REG3 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x23))) // RW/RW, data buffer 3
  78. #define R32_DATA_REG4_7 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x24))) // RW/RW, data buffer 4~7
  79. #define R8_DATA_REG4 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x24))) // RW/RW, data buffer 4
  80. #define R8_DATA_REG5 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x25))) // RW/RW, data buffer 5
  81. #define R8_DATA_REG6 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x26))) // RW/RW, data buffer 6
  82. #define R8_DATA_REG7 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x27))) // RW/RW, data buffer 7
  83. #define R32_DATA_REG8_11 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x28))) // RW/RW, data buffer 8~11
  84. #define R8_DATA_REG8 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x28))) // RW/RW, data buffer 8
  85. #define R8_DATA_REG9 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x29))) // RW/RW, data buffer 9
  86. #define R8_DATA_REG10 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2A))) // RW/RW, data buffer 10
  87. #define R8_DATA_REG11 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2B))) // RW/RW, data buffer 11
  88. #define R32_DATA_REG12_15 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x2C))) // RW/RW, data buffer 12~15
  89. #define R8_DATA_REG12 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2C))) // RW/RW, data buffer 12
  90. #define R8_DATA_REG13 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2D))) // RW/RW, data buffer 13
  91. #define R8_DATA_REG14 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2E))) // RW/RW, data buffer 14
  92. #define R8_DATA_REG15 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2F))) // RW/RW, data buffer 15
  93. #define R32_DATA_REG16_19 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x30))) // RW/RW, data buffer 16~19
  94. #define R8_DATA_REG16 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x30))) // RW/RW, data buffer 16
  95. #define R8_DATA_REG17 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x31))) // RW/RW, data buffer 17
  96. #define R8_DATA_REG18 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x32))) // RW/RW, data buffer 18
  97. #define R8_DATA_REG19 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x33))) // RW/RW, data buffer 19
  98. #define R32_DATA_REG20_23 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x34))) // RW/RW, data buffer 20~23
  99. #define R8_DATA_REG20 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x34))) // RW/RW, data buffer 20
  100. #define R8_DATA_REG21 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x35))) // RW/RW, data buffer 21
  101. #define R8_DATA_REG22 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x36))) // RW/RW, data buffer 22
  102. #define R8_DATA_REG23 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x37))) // RW/RW, data buffer 23
  103. #define R32_DATA_REG24_27 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x38))) // RW/RW, data buffer 24~27
  104. #define R8_DATA_REG24 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x38))) // RW/RW, data buffer 24
  105. #define R8_DATA_REG25 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x39))) // RW/RW, data buffer 25
  106. #define R8_DATA_REG26 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3A))) // RW/RW, data buffer 26
  107. #define R8_DATA_REG27 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3B))) // RW/RW, data buffer 27
  108. #define R32_DATA_REG28_31 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x3C))) // RW/RW, data buffer 28~31
  109. #define R8_DATA_REG28 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3C))) // RW/RW, data buffer 28
  110. #define R8_DATA_REG29 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3D))) // RW/RW, data buffer 29
  111. #define R8_DATA_REG30 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3E))) // RW/RW, data buffer 30
  112. #define R8_DATA_REG31 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3F))) // RW/RW, data buffer 31
  113. /* ******************************************************************************************************* */
  114. /* PIOC Registers */
  115. typedef struct
  116. {
  117. uint32_t RESERVED00;
  118. union {
  119. __IO uint32_t D32_PIOC_SFR ; // RO/RW, PIOC SFR
  120. struct {
  121. __IO uint8_t D8_INDIR_ADDR; // RO/RW, PIOC indirect address
  122. __IO uint8_t D8_TMR0_COUNT; // RO/RW, PIOC timer count
  123. __IO uint8_t D8_TMR0_CTRL; // RO/RW, PIOC timer control and GP bit
  124. __IO uint8_t D8_TMR0_INIT; // RO/RW, PIOC timer initial value
  125. } ;
  126. } ;
  127. union {
  128. __IO uint32_t D32_PORT_CFG ; // RO/RW, port status and config
  129. struct {
  130. __IO uint8_t D8_BIT_CYCLE; // RO/RW, encode bit cycle
  131. __IO uint8_t D8_INDIR_ADDR2; // RO/RW, PIOC indirect address 2
  132. __IO uint8_t D8_PORT_DIR; // RO/RW, IO port direction and mode
  133. __IO uint8_t D8_PORT_IO; // RO/RW, IO port input and output
  134. } ;
  135. } ;
  136. uint32_t RESERVED0C;
  137. uint32_t RESERVED10;
  138. uint32_t RESERVED14;
  139. uint32_t RESERVED18;
  140. union {
  141. __IO uint32_t D32_DATA_CTRL ; // RW/RW, data control
  142. struct {
  143. __IO uint8_t D8_SYS_CFG; // RW/RW, port config
  144. __IO uint8_t D8_CTRL_RD; // RO/RW, data for master read only and PIOC write only
  145. __IO uint8_t D8_CTRL_WR; // RW/RO, data for master write only and PIOC read only
  146. __IO uint8_t D8_DATA_EXCH; // RW/RW, data exchange
  147. } ;
  148. } ;
  149. union {
  150. __IO uint32_t D32_DATA_REG0_3 ; // RW/RW, data buffer 0~3
  151. struct {
  152. __IO uint8_t D8_DATA_REG0; // RW/RW, data buffer 0
  153. __IO uint8_t D8_DATA_REG1; // RW/RW, data buffer 1
  154. __IO uint8_t D8_DATA_REG2; // RW/RW, data buffer 2
  155. __IO uint8_t D8_DATA_REG3; // RW/RW, data buffer 3
  156. } ;
  157. __IO uint16_t D16_DATA_REG0_1 ; // RW/RW, data buffer 0~1
  158. } ;
  159. union {
  160. __IO uint32_t D32_DATA_REG4_7 ; // RW/RW, data buffer 4~7
  161. struct {
  162. __IO uint8_t D8_DATA_REG4; // RW/RW, data buffer 4
  163. __IO uint8_t D8_DATA_REG5; // RW/RW, data buffer 5
  164. __IO uint8_t D8_DATA_REG6; // RW/RW, data buffer 6
  165. __IO uint8_t D8_DATA_REG7; // RW/RW, data buffer 7
  166. } ;
  167. } ;
  168. union {
  169. __IO uint32_t D32_DATA_REG8_11 ; // RW/RW, data buffer 8~11
  170. struct {
  171. __IO uint8_t D8_DATA_REG8; // RW/RW, data buffer 8
  172. __IO uint8_t D8_DATA_REG9; // RW/RW, data buffer 9
  173. __IO uint8_t D8_DATA_REG10; // RW/RW, data buffer 10
  174. __IO uint8_t D8_DATA_REG11; // RW/RW, data buffer 11
  175. } ;
  176. } ;
  177. union {
  178. __IO uint32_t D32_DATA_REG12_15 ; // RW/RW, data buffer 12~15
  179. struct {
  180. __IO uint8_t D8_DATA_REG12; // RW/RW, data buffer 12
  181. __IO uint8_t D8_DATA_REG13; // RW/RW, data buffer 13
  182. __IO uint8_t D8_DATA_REG14; // RW/RW, data buffer 14
  183. __IO uint8_t D8_DATA_REG15; // RW/RW, data buffer 15
  184. } ;
  185. } ;
  186. union {
  187. __IO uint32_t D32_DATA_REG16_19 ; // RW/RW, data buffer 16~19
  188. struct {
  189. __IO uint8_t D8_DATA_REG16; // RW/RW, data buffer 16
  190. __IO uint8_t D8_DATA_REG17; // RW/RW, data buffer 17
  191. __IO uint8_t D8_DATA_REG18; // RW/RW, data buffer 18
  192. __IO uint8_t D8_DATA_REG19; // RW/RW, data buffer 19
  193. } ;
  194. } ;
  195. union {
  196. __IO uint32_t D32_DATA_REG20_23 ; // RW/RW, data buffer 20~23
  197. struct {
  198. __IO uint8_t D8_DATA_REG20; // RW/RW, data buffer 20
  199. __IO uint8_t D8_DATA_REG21; // RW/RW, data buffer 21
  200. __IO uint8_t D8_DATA_REG22; // RW/RW, data buffer 22
  201. __IO uint8_t D8_DATA_REG23; // RW/RW, data buffer 23
  202. } ;
  203. } ;
  204. union {
  205. __IO uint32_t D32_DATA_REG24_27 ; // RW/RW, data buffer 24~27
  206. struct {
  207. __IO uint8_t D8_DATA_REG24; // RW/RW, data buffer 24
  208. __IO uint8_t D8_DATA_REG25; // RW/RW, data buffer 25
  209. __IO uint8_t D8_DATA_REG26; // RW/RW, data buffer 26
  210. __IO uint8_t D8_DATA_REG27; // RW/RW, data buffer 27
  211. } ;
  212. } ;
  213. union {
  214. __IO uint32_t D32_DATA_REG28_31 ; // RW/RW, data buffer 28~31
  215. struct {
  216. __IO uint8_t D8_DATA_REG28; // RW/RW, data buffer 28
  217. __IO uint8_t D8_DATA_REG29; // RW/RW, data buffer 29
  218. __IO uint8_t D8_DATA_REG30; // RW/RW, data buffer 30
  219. __IO uint8_t D8_DATA_REG31; // RW/RW, data buffer 31
  220. } ;
  221. } ;
  222. } PIOC_TypeDef;
  223. #define PIOC ((PIOC_TypeDef *)PIOC_BASE)
  224. #ifdef __cplusplus
  225. }
  226. #endif
  227. #endif // __PIOC_SFR_H__