ch32v30x.h 478 KB

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  1. /********************************** (C) COPYRIGHT *******************************
  2. * File Name : ch32v30x.h
  3. * Author : WCH
  4. * Version : V1.0.1
  5. * Date : 2025/04/09
  6. * Description : CH32V30x Device Peripheral Access Layer Header File.
  7. *********************************************************************************
  8. * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
  9. * Attention: This software (modified or not) and binary are used for
  10. * microcontroller manufactured by Nanjing Qinheng Microelectronics.
  11. *******************************************************************************/
  12. #ifndef __CH32V30x_H
  13. #define __CH32V30x_H
  14. #ifdef __cplusplus
  15. extern "C" {
  16. #endif
  17. #if !defined(CH32V30x_D8) && !defined(CH32V30x_D8C)
  18. //#define CH32V30x_D8 /* CH32V303x */
  19. #define CH32V30x_D8C /* CH32V307x-CH32V305x-CH32V317x */
  20. #endif
  21. #define __MPU_PRESENT 0 /* Other CH32 devices does not provide an MPU */
  22. #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
  23. #ifndef HSE_VALUE
  24. #define HSE_VALUE ((uint32_t)8000000) /* Value of the External oscillator in Hz */
  25. #endif
  26. /* In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value */
  27. #define HSE_STARTUP_TIMEOUT ((uint16_t)0x1000) /* Time out for HSE start up */
  28. #define HSI_VALUE ((uint32_t)8000000) /* Value of the Internal oscillator in Hz */
  29. /* CH32V30x Standard Peripheral Library version number */
  30. #define __CH32V30x_STDPERIPH_VERSION_MAIN (0x02) /* [15:8] main version */
  31. #define __CH32V30x_STDPERIPH_VERSION_SUB (0x08) /* [7:0] sub version */
  32. #define __CH32V30x_STDPERIPH_VERSION ( (__CH32V30x_STDPERIPH_VERSION_MAIN << 8)\
  33. |(__CH32V30x_STDPERIPH_VERSION_SUB << 0))
  34. /* Interrupt Number Definition, according to the selected device */
  35. typedef enum IRQn
  36. {
  37. /****** RISC-V Processor Exceptions Numbers *******************************************************/
  38. NonMaskableInt_IRQn = 2, /* 2 Non Maskable Interrupt */
  39. EXC_IRQn = 3, /* 3 Exception Interrupt */
  40. Ecall_M_Mode_IRQn = 5, /* 5 Ecall M Mode Interrupt */
  41. Ecall_U_Mode_IRQn = 8, /* 8 Ecall U Mode Interrupt */
  42. Break_Point_IRQn = 9, /* 9 Break Point Interrupt */
  43. SysTick_IRQn = 12, /* 12 System timer Interrupt */
  44. Software_IRQn = 14, /* 14 software Interrupt */
  45. /****** RISC-V specific Interrupt Numbers *********************************************************/
  46. WWDG_IRQn = 16, /* Window WatchDog Interrupt */
  47. PVD_IRQn = 17, /* PVD through EXTI Line detection Interrupt */
  48. TAMPER_IRQn = 18, /* Tamper Interrupt */
  49. RTC_IRQn = 19, /* RTC global Interrupt */
  50. FLASH_IRQn = 20, /* FLASH global Interrupt */
  51. RCC_IRQn = 21, /* RCC global Interrupt */
  52. EXTI0_IRQn = 22, /* EXTI Line0 Interrupt */
  53. EXTI1_IRQn = 23, /* EXTI Line1 Interrupt */
  54. EXTI2_IRQn = 24, /* EXTI Line2 Interrupt */
  55. EXTI3_IRQn = 25, /* EXTI Line3 Interrupt */
  56. EXTI4_IRQn = 26, /* EXTI Line4 Interrupt */
  57. DMA1_Channel1_IRQn = 27, /* DMA1 Channel 1 global Interrupt */
  58. DMA1_Channel2_IRQn = 28, /* DMA1 Channel 2 global Interrupt */
  59. DMA1_Channel3_IRQn = 29, /* DMA1 Channel 3 global Interrupt */
  60. DMA1_Channel4_IRQn = 30, /* DMA1 Channel 4 global Interrupt */
  61. DMA1_Channel5_IRQn = 31, /* DMA1 Channel 5 global Interrupt */
  62. DMA1_Channel6_IRQn = 32, /* DMA1 Channel 6 global Interrupt */
  63. DMA1_Channel7_IRQn = 33, /* DMA1 Channel 7 global Interrupt */
  64. ADC_IRQn = 34, /* ADC1 and ADC2 global Interrupt */
  65. USB_HP_CAN1_TX_IRQn = 35, /* USB Device High Priority or CAN1 TX Interrupts */
  66. USB_LP_CAN1_RX0_IRQn = 36, /* USB Device Low Priority or CAN1 RX0 Interrupts */
  67. CAN1_RX1_IRQn = 37, /* CAN1 RX1 Interrupt */
  68. CAN1_SCE_IRQn = 38, /* CAN1 SCE Interrupt */
  69. EXTI9_5_IRQn = 39, /* External Line[9:5] Interrupts */
  70. TIM1_BRK_IRQn = 40, /* TIM1 Break Interrupt */
  71. TIM1_UP_IRQn = 41, /* TIM1 Update Interrupt */
  72. TIM1_TRG_COM_IRQn = 42, /* TIM1 Trigger and Commutation Interrupt */
  73. TIM1_CC_IRQn = 43, /* TIM1 Capture Compare Interrupt */
  74. TIM2_IRQn = 44, /* TIM2 global Interrupt */
  75. TIM3_IRQn = 45, /* TIM3 global Interrupt */
  76. TIM4_IRQn = 46, /* TIM4 global Interrupt */
  77. I2C1_EV_IRQn = 47, /* I2C1 Event Interrupt */
  78. I2C1_ER_IRQn = 48, /* I2C1 Error Interrupt */
  79. I2C2_EV_IRQn = 49, /* I2C2 Event Interrupt */
  80. I2C2_ER_IRQn = 50, /* I2C2 Error Interrupt */
  81. SPI1_IRQn = 51, /* SPI1 global Interrupt */
  82. SPI2_IRQn = 52, /* SPI2 global Interrupt */
  83. USART1_IRQn = 53, /* USART1 global Interrupt */
  84. USART2_IRQn = 54, /* USART2 global Interrupt */
  85. USART3_IRQn = 55, /* USART3 global Interrupt */
  86. EXTI15_10_IRQn = 56, /* External Line[15:10] Interrupts */
  87. RTCAlarm_IRQn = 57, /* RTC Alarm through EXTI Line Interrupt */
  88. #ifdef CH32V30x_D8
  89. TIM8_BRK_IRQn = 59, /* TIM8 Break Interrupt */
  90. TIM8_UP_IRQn = 60, /* TIM8 Update Interrupt */
  91. TIM8_TRG_COM_IRQn = 61, /* TIM8 Trigger and Commutation Interrupt */
  92. TIM8_CC_IRQn = 62, /* TIM8 Capture Compare Interrupt */
  93. RNG_IRQn = 63, /* RNG global Interrupt */
  94. SDIO_IRQn = 65, /* SDIO global Interrupt */
  95. TIM5_IRQn = 66, /* TIM5 global Interrupt */
  96. SPI3_IRQn = 67, /* SPI3 global Interrupt */
  97. UART4_IRQn = 68, /* UART4 global Interrupt */
  98. UART5_IRQn = 69, /* UART5 global Interrupt */
  99. TIM6_IRQn = 70, /* TIM6 global Interrupt */
  100. TIM7_IRQn = 71, /* TIM7 global Interrupt */
  101. DMA2_Channel1_IRQn = 72, /* DMA2 Channel 1 global Interrupt */
  102. DMA2_Channel2_IRQn = 73, /* DMA2 Channel 2 global Interrupt */
  103. DMA2_Channel3_IRQn = 74, /* DMA2 Channel 3 global Interrupt */
  104. DMA2_Channel4_IRQn = 75, /* DMA2 Channel 4 global Interrupt */
  105. DMA2_Channel5_IRQn = 76, /* DMA2 Channel 5 global Interrupt */
  106. USBFS_IRQn = 83, /* USBFS global Interrupt */
  107. UART6_IRQn = 87, /* UART6 global Interrupt */
  108. UART7_IRQn = 88, /* UART7 global Interrupt */
  109. UART8_IRQn = 89, /* UART8 global Interrupt */
  110. TIM9_BRK_IRQn = 90, /* TIM9 Break Interrupt */
  111. TIM9_UP_IRQn = 91, /* TIM9 Update Interrupt */
  112. TIM9_TRG_COM_IRQn = 92, /* TIM9 Trigger and Commutation Interrupt */
  113. TIM9_CC_IRQn = 93, /* TIM9 Capture Compare Interrupt */
  114. TIM10_BRK_IRQn = 94, /* TIM10 Break Interrupt */
  115. TIM10_UP_IRQn = 95, /* TIM10 Update Interrupt */
  116. TIM10_TRG_COM_IRQn = 96, /* TIM10 Trigger and Commutation Interrupt */
  117. TIM10_CC_IRQn = 97, /* TIM10 Capture Compare Interrupt */
  118. DMA2_Channel6_IRQn = 98, /* DMA2 Channel 6 global Interrupt */
  119. DMA2_Channel7_IRQn = 99, /* DMA2 Channel 7 global Interrupt */
  120. DMA2_Channel8_IRQn = 100, /* DMA2 Channel 8 global Interrupt */
  121. DMA2_Channel9_IRQn = 101, /* DMA2 Channel 9 global Interrupt */
  122. DMA2_Channel10_IRQn = 102, /* DMA2 Channel 10 global Interrupt */
  123. DMA2_Channel11_IRQn = 103, /* DMA2 Channel 11 global Interrupt */
  124. #elif defined (CH32V30x_D8C)
  125. USBWakeUp_IRQn = 58, /* USB Device WakeUp from suspend through EXTI Line Interrupt */
  126. TIM8_BRK_IRQn = 59, /* TIM8 Break Interrupt */
  127. TIM8_UP_IRQn = 60, /* TIM8 Update Interrupt */
  128. TIM8_TRG_COM_IRQn = 61, /* TIM8 Trigger and Commutation Interrupt */
  129. TIM8_CC_IRQn = 62, /* TIM8 Capture Compare Interrupt */
  130. RNG_IRQn = 63, /* RNG global Interrupt */
  131. SDIO_IRQn = 65, /* SDIO global Interrupt */
  132. TIM5_IRQn = 66, /* TIM5 global Interrupt */
  133. SPI3_IRQn = 67, /* SPI3 global Interrupt */
  134. UART4_IRQn = 68, /* UART4 global Interrupt */
  135. UART5_IRQn = 69, /* UART5 global Interrupt */
  136. TIM6_IRQn = 70, /* TIM6 global Interrupt */
  137. TIM7_IRQn = 71, /* TIM7 global Interrupt */
  138. DMA2_Channel1_IRQn = 72, /* DMA2 Channel 1 global Interrupt */
  139. DMA2_Channel2_IRQn = 73, /* DMA2 Channel 2 global Interrupt */
  140. DMA2_Channel3_IRQn = 74, /* DMA2 Channel 3 global Interrupt */
  141. DMA2_Channel4_IRQn = 75, /* DMA2 Channel 4 global Interrupt */
  142. DMA2_Channel5_IRQn = 76, /* DMA2 Channel 5 global Interrupt */
  143. ETH_IRQn = 77, /* ETH global Interrupt */
  144. ETH_WKUP_IRQn = 78, /* ETH WakeUp Interrupt */
  145. CAN2_TX_IRQn = 79, /* CAN2 TX Interrupts */
  146. CAN2_RX0_IRQn = 80, /* CAN2 RX0 Interrupts */
  147. CAN2_RX1_IRQn = 81, /* CAN2 RX1 Interrupt */
  148. CAN2_SCE_IRQn = 82, /* CAN2 SCE Interrupt */
  149. USBFS_IRQn = 83, /* USBFS global Interrupt */
  150. USBHSWakeup_IRQn = 84, /* USBHS WakeUp Interrupt */
  151. USBHS_IRQn = 85, /* USBHS global Interrupt */
  152. DVP_IRQn = 86, /* DVP global Interrupt */
  153. UART6_IRQn = 87, /* UART6 global Interrupt */
  154. UART7_IRQn = 88, /* UART7 global Interrupt */
  155. UART8_IRQn = 89, /* UART8 global Interrupt */
  156. TIM9_BRK_IRQn = 90, /* TIM9 Break Interrupt */
  157. TIM9_UP_IRQn = 91, /* TIM9 Update Interrupt */
  158. TIM9_TRG_COM_IRQn = 92, /* TIM9 Trigger and Commutation Interrupt */
  159. TIM9_CC_IRQn = 93, /* TIM9 Capture Compare Interrupt */
  160. TIM10_BRK_IRQn = 94, /* TIM10 Break Interrupt */
  161. TIM10_UP_IRQn = 95, /* TIM10 Update Interrupt */
  162. TIM10_TRG_COM_IRQn = 96, /* TIM10 Trigger and Commutation Interrupt */
  163. TIM10_CC_IRQn = 97, /* TIM10 Capture Compare Interrupt */
  164. DMA2_Channel6_IRQn = 98, /* DMA2 Channel 6 global Interrupt */
  165. DMA2_Channel7_IRQn = 99, /* DMA2 Channel 7 global Interrupt */
  166. DMA2_Channel8_IRQn = 100, /* DMA2 Channel 8 global Interrupt */
  167. DMA2_Channel9_IRQn = 101, /* DMA2 Channel 9 global Interrupt */
  168. DMA2_Channel10_IRQn = 102, /* DMA2 Channel 10 global Interrupt */
  169. DMA2_Channel11_IRQn = 103, /* DMA2 Channel 11 global Interrupt */
  170. #endif
  171. } IRQn_Type;
  172. #define HardFault_IRQn EXC_IRQn
  173. #define ADC1_2_IRQn ADC_IRQn
  174. #define SysTicK_IRQn SysTick_IRQn
  175. #define OTG_FS_IRQn USBFS_IRQn
  176. #define OTG_FS_IRQHandler USBFS_IRQHandler
  177. #define USBHD_IRQHandler USBFS_IRQHandler
  178. #define USBOTG_FS USBFSD
  179. #define USBOTG_H_FS USBFSH
  180. #include <stdint.h>
  181. #include "core_riscv.h"
  182. #include "system_ch32v30x.h"
  183. /* Standard Peripheral Library old definitions (maintained for legacy purpose) */
  184. #define HSI_Value HSI_VALUE
  185. #define HSE_Value HSE_VALUE
  186. #define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT
  187. /* Analog to Digital Converter */
  188. typedef struct
  189. {
  190. __IO uint32_t STATR;
  191. __IO uint32_t CTLR1;
  192. __IO uint32_t CTLR2;
  193. __IO uint32_t SAMPTR1;
  194. __IO uint32_t SAMPTR2;
  195. __IO uint32_t IOFR1;
  196. __IO uint32_t IOFR2;
  197. __IO uint32_t IOFR3;
  198. __IO uint32_t IOFR4;
  199. __IO uint32_t WDHTR;
  200. __IO uint32_t WDLTR;
  201. __IO uint32_t RSQR1;
  202. __IO uint32_t RSQR2;
  203. __IO uint32_t RSQR3;
  204. __IO uint32_t ISQR;
  205. __IO uint32_t IDATAR1;
  206. __IO uint32_t IDATAR2;
  207. __IO uint32_t IDATAR3;
  208. __IO uint32_t IDATAR4;
  209. __IO uint32_t RDATAR;
  210. uint32_t RESERVED0;
  211. __IO uint32_t AUX;
  212. } ADC_TypeDef;
  213. /* Backup Registers */
  214. typedef struct
  215. {
  216. uint32_t RESERVED0;
  217. __IO uint16_t DATAR1;
  218. uint16_t RESERVED1;
  219. __IO uint16_t DATAR2;
  220. uint16_t RESERVED2;
  221. __IO uint16_t DATAR3;
  222. uint16_t RESERVED3;
  223. __IO uint16_t DATAR4;
  224. uint16_t RESERVED4;
  225. __IO uint16_t DATAR5;
  226. uint16_t RESERVED5;
  227. __IO uint16_t DATAR6;
  228. uint16_t RESERVED6;
  229. __IO uint16_t DATAR7;
  230. uint16_t RESERVED7;
  231. __IO uint16_t DATAR8;
  232. uint16_t RESERVED8;
  233. __IO uint16_t DATAR9;
  234. uint16_t RESERVED9;
  235. __IO uint16_t DATAR10;
  236. uint16_t RESERVED10;
  237. __IO uint16_t OCTLR;
  238. uint16_t RESERVED11;
  239. __IO uint16_t TPCTLR;
  240. uint16_t RESERVED12;
  241. __IO uint16_t TPCSR;
  242. uint16_t RESERVED13[5];
  243. __IO uint16_t DATAR11;
  244. uint16_t RESERVED14;
  245. __IO uint16_t DATAR12;
  246. uint16_t RESERVED15;
  247. __IO uint16_t DATAR13;
  248. uint16_t RESERVED16;
  249. __IO uint16_t DATAR14;
  250. uint16_t RESERVED17;
  251. __IO uint16_t DATAR15;
  252. uint16_t RESERVED18;
  253. __IO uint16_t DATAR16;
  254. uint16_t RESERVED19;
  255. __IO uint16_t DATAR17;
  256. uint16_t RESERVED20;
  257. __IO uint16_t DATAR18;
  258. uint16_t RESERVED21;
  259. __IO uint16_t DATAR19;
  260. uint16_t RESERVED22;
  261. __IO uint16_t DATAR20;
  262. uint16_t RESERVED23;
  263. __IO uint16_t DATAR21;
  264. uint16_t RESERVED24;
  265. __IO uint16_t DATAR22;
  266. uint16_t RESERVED25;
  267. __IO uint16_t DATAR23;
  268. uint16_t RESERVED26;
  269. __IO uint16_t DATAR24;
  270. uint16_t RESERVED27;
  271. __IO uint16_t DATAR25;
  272. uint16_t RESERVED28;
  273. __IO uint16_t DATAR26;
  274. uint16_t RESERVED29;
  275. __IO uint16_t DATAR27;
  276. uint16_t RESERVED30;
  277. __IO uint16_t DATAR28;
  278. uint16_t RESERVED31;
  279. __IO uint16_t DATAR29;
  280. uint16_t RESERVED32;
  281. __IO uint16_t DATAR30;
  282. uint16_t RESERVED33;
  283. __IO uint16_t DATAR31;
  284. uint16_t RESERVED34;
  285. __IO uint16_t DATAR32;
  286. uint16_t RESERVED35;
  287. __IO uint16_t DATAR33;
  288. uint16_t RESERVED36;
  289. __IO uint16_t DATAR34;
  290. uint16_t RESERVED37;
  291. __IO uint16_t DATAR35;
  292. uint16_t RESERVED38;
  293. __IO uint16_t DATAR36;
  294. uint16_t RESERVED39;
  295. __IO uint16_t DATAR37;
  296. uint16_t RESERVED40;
  297. __IO uint16_t DATAR38;
  298. uint16_t RESERVED41;
  299. __IO uint16_t DATAR39;
  300. uint16_t RESERVED42;
  301. __IO uint16_t DATAR40;
  302. uint16_t RESERVED43;
  303. __IO uint16_t DATAR41;
  304. uint16_t RESERVED44;
  305. __IO uint16_t DATAR42;
  306. uint16_t RESERVED45;
  307. } BKP_TypeDef;
  308. /* Controller Area Network TxMailBox */
  309. typedef struct
  310. {
  311. __IO uint32_t TXMIR;
  312. __IO uint32_t TXMDTR;
  313. __IO uint32_t TXMDLR;
  314. __IO uint32_t TXMDHR;
  315. } CAN_TxMailBox_TypeDef;
  316. /* Controller Area Network FIFOMailBox */
  317. typedef struct
  318. {
  319. __IO uint32_t RXMIR;
  320. __IO uint32_t RXMDTR;
  321. __IO uint32_t RXMDLR;
  322. __IO uint32_t RXMDHR;
  323. } CAN_FIFOMailBox_TypeDef;
  324. /* Controller Area Network FilterRegister */
  325. typedef struct
  326. {
  327. __IO uint32_t FR1;
  328. __IO uint32_t FR2;
  329. } CAN_FilterRegister_TypeDef;
  330. /* Controller Area Network */
  331. typedef struct
  332. {
  333. __IO uint32_t CTLR;
  334. __IO uint32_t STATR;
  335. __IO uint32_t TSTATR;
  336. __IO uint32_t RFIFO0;
  337. __IO uint32_t RFIFO1;
  338. __IO uint32_t INTENR;
  339. __IO uint32_t ERRSR;
  340. __IO uint32_t BTIMR;
  341. uint32_t RESERVED0[88];
  342. CAN_TxMailBox_TypeDef sTxMailBox[3];
  343. CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
  344. uint32_t RESERVED1[12];
  345. __IO uint32_t FCTLR;
  346. __IO uint32_t FMCFGR;
  347. uint32_t RESERVED2;
  348. __IO uint32_t FSCFGR;
  349. uint32_t RESERVED3;
  350. __IO uint32_t FAFIFOR;
  351. uint32_t RESERVED4;
  352. __IO uint32_t FWR;
  353. uint32_t RESERVED5[8];
  354. CAN_FilterRegister_TypeDef sFilterRegister[28];
  355. } CAN_TypeDef;
  356. /* CRC Calculation Unit */
  357. typedef struct
  358. {
  359. __IO uint32_t DATAR;
  360. __IO uint8_t IDATAR;
  361. uint8_t RESERVED0;
  362. uint16_t RESERVED1;
  363. __IO uint32_t CTLR;
  364. } CRC_TypeDef;
  365. /* Digital to Analog Converter */
  366. typedef struct
  367. {
  368. __IO uint32_t CTLR;
  369. __IO uint32_t SWTR;
  370. __IO uint32_t R12BDHR1;
  371. __IO uint32_t L12BDHR1;
  372. __IO uint32_t R8BDHR1;
  373. __IO uint32_t R12BDHR2;
  374. __IO uint32_t L12BDHR2;
  375. __IO uint32_t R8BDHR2;
  376. __IO uint32_t RD12BDHR;
  377. __IO uint32_t LD12BDHR;
  378. __IO uint32_t RD8BDHR;
  379. __IO uint32_t DOR1;
  380. __IO uint32_t DOR2;
  381. } DAC_TypeDef;
  382. /* DMA Channel Controller */
  383. typedef struct
  384. {
  385. __IO uint32_t CFGR;
  386. __IO uint32_t CNTR;
  387. __IO uint32_t PADDR;
  388. __IO uint32_t MADDR;
  389. } DMA_Channel_TypeDef;
  390. /* DMA Controller */
  391. typedef struct
  392. {
  393. __IO uint32_t INTFR;
  394. __IO uint32_t INTFCR;
  395. } DMA_TypeDef;
  396. /* External Interrupt/Event Controller */
  397. typedef struct
  398. {
  399. __IO uint32_t INTENR;
  400. __IO uint32_t EVENR;
  401. __IO uint32_t RTENR;
  402. __IO uint32_t FTENR;
  403. __IO uint32_t SWIEVR;
  404. __IO uint32_t INTFR;
  405. } EXTI_TypeDef;
  406. /* FLASH Registers */
  407. typedef struct
  408. {
  409. __IO uint32_t ACTLR;
  410. __IO uint32_t KEYR;
  411. __IO uint32_t OBKEYR;
  412. __IO uint32_t STATR;
  413. __IO uint32_t CTLR;
  414. __IO uint32_t ADDR;
  415. __IO uint32_t RESERVED;
  416. __IO uint32_t OBR;
  417. __IO uint32_t WPR;
  418. __IO uint32_t MODEKEYR;
  419. } FLASH_TypeDef;
  420. /* Option Bytes Registers */
  421. typedef struct
  422. {
  423. __IO uint16_t RDPR;
  424. __IO uint16_t USER;
  425. __IO uint16_t Data0;
  426. __IO uint16_t Data1;
  427. __IO uint16_t WRPR0;
  428. __IO uint16_t WRPR1;
  429. __IO uint16_t WRPR2;
  430. __IO uint16_t WRPR3;
  431. } OB_TypeDef;
  432. /* FSMC Bank1 Registers */
  433. typedef struct
  434. {
  435. __IO uint32_t BTCR[8];
  436. } FSMC_Bank1_TypeDef;
  437. /* FSMC Bank1E Registers */
  438. typedef struct
  439. {
  440. __IO uint32_t BWTR[7];
  441. } FSMC_Bank1E_TypeDef;
  442. /* FSMC Bank2 Registers */
  443. typedef struct
  444. {
  445. __IO uint32_t PCR2;
  446. __IO uint32_t SR2;
  447. __IO uint32_t PMEM2;
  448. __IO uint32_t PATT2;
  449. uint32_t RESERVED0;
  450. __IO uint32_t ECCR2;
  451. } FSMC_Bank2_TypeDef;
  452. /* General Purpose I/O */
  453. typedef struct
  454. {
  455. __IO uint32_t CFGLR;
  456. __IO uint32_t CFGHR;
  457. __IO uint32_t INDR;
  458. __IO uint32_t OUTDR;
  459. __IO uint32_t BSHR;
  460. __IO uint32_t BCR;
  461. __IO uint32_t LCKR;
  462. } GPIO_TypeDef;
  463. /* Alternate Function I/O */
  464. typedef struct
  465. {
  466. __IO uint32_t ECR;
  467. __IO uint32_t PCFR1;
  468. __IO uint32_t EXTICR[4];
  469. uint32_t RESERVED0;
  470. __IO uint32_t PCFR2;
  471. } AFIO_TypeDef;
  472. /* Inter Integrated Circuit Interface */
  473. typedef struct
  474. {
  475. __IO uint16_t CTLR1;
  476. uint16_t RESERVED0;
  477. __IO uint16_t CTLR2;
  478. uint16_t RESERVED1;
  479. __IO uint16_t OADDR1;
  480. uint16_t RESERVED2;
  481. __IO uint16_t OADDR2;
  482. uint16_t RESERVED3;
  483. __IO uint16_t DATAR;
  484. uint16_t RESERVED4;
  485. __IO uint16_t STAR1;
  486. uint16_t RESERVED5;
  487. __IO uint16_t STAR2;
  488. uint16_t RESERVED6;
  489. __IO uint16_t CKCFGR;
  490. uint16_t RESERVED7;
  491. __IO uint16_t RTR;
  492. uint16_t RESERVED8;
  493. } I2C_TypeDef;
  494. /* Independent WatchDog */
  495. typedef struct
  496. {
  497. __IO uint32_t CTLR;
  498. __IO uint32_t PSCR;
  499. __IO uint32_t RLDR;
  500. __IO uint32_t STATR;
  501. } IWDG_TypeDef;
  502. /* Power Control */
  503. typedef struct
  504. {
  505. __IO uint32_t CTLR;
  506. __IO uint32_t CSR;
  507. } PWR_TypeDef;
  508. /* Reset and Clock Control */
  509. typedef struct
  510. {
  511. __IO uint32_t CTLR;
  512. __IO uint32_t CFGR0;
  513. __IO uint32_t INTR;
  514. __IO uint32_t APB2PRSTR;
  515. __IO uint32_t APB1PRSTR;
  516. __IO uint32_t AHBPCENR;
  517. __IO uint32_t APB2PCENR;
  518. __IO uint32_t APB1PCENR;
  519. __IO uint32_t BDCTLR;
  520. __IO uint32_t RSTSCKR;
  521. __IO uint32_t AHBRSTR;
  522. __IO uint32_t CFGR2;
  523. } RCC_TypeDef;
  524. /* Real-Time Clock */
  525. typedef struct
  526. {
  527. __IO uint16_t CTLRH;
  528. uint16_t RESERVED0;
  529. __IO uint16_t CTLRL;
  530. uint16_t RESERVED1;
  531. __IO uint16_t PSCRH;
  532. uint16_t RESERVED2;
  533. __IO uint16_t PSCRL;
  534. uint16_t RESERVED3;
  535. __IO uint16_t DIVH;
  536. uint16_t RESERVED4;
  537. __IO uint16_t DIVL;
  538. uint16_t RESERVED5;
  539. __IO uint16_t CNTH;
  540. uint16_t RESERVED6;
  541. __IO uint16_t CNTL;
  542. uint16_t RESERVED7;
  543. __IO uint16_t ALRMH;
  544. uint16_t RESERVED8;
  545. __IO uint16_t ALRML;
  546. uint16_t RESERVED9;
  547. } RTC_TypeDef;
  548. /* SDIO Registers */
  549. typedef struct
  550. {
  551. __IO uint32_t POWER;
  552. __IO uint32_t CLKCR;
  553. __IO uint32_t ARG;
  554. __IO uint32_t CMD;
  555. __I uint32_t RESPCMD;
  556. __I uint32_t RESP1;
  557. __I uint32_t RESP2;
  558. __I uint32_t RESP3;
  559. __I uint32_t RESP4;
  560. __IO uint32_t DTIMER;
  561. __IO uint32_t DLEN;
  562. __IO uint32_t DCTRL;
  563. __I uint32_t DCOUNT;
  564. __I uint32_t STA;
  565. __IO uint32_t ICR;
  566. __IO uint32_t MASK;
  567. uint32_t RESERVED0[2];
  568. __I uint32_t FIFOCNT;
  569. uint32_t RESERVED1[5];
  570. __IO uint32_t DCTRL2;
  571. uint32_t RESERVED2[7];
  572. __IO uint32_t FIFO;
  573. } SDIO_TypeDef;
  574. /* Serial Peripheral Interface */
  575. typedef struct
  576. {
  577. __IO uint16_t CTLR1;
  578. uint16_t RESERVED0;
  579. __IO uint16_t CTLR2;
  580. uint16_t RESERVED1;
  581. __IO uint16_t STATR;
  582. uint16_t RESERVED2;
  583. __IO uint16_t DATAR;
  584. uint16_t RESERVED3;
  585. __IO uint16_t CRCR;
  586. uint16_t RESERVED4;
  587. __IO uint16_t RCRCR;
  588. uint16_t RESERVED5;
  589. __IO uint16_t TCRCR;
  590. uint16_t RESERVED6;
  591. __IO uint16_t I2SCFGR;
  592. uint16_t RESERVED7;
  593. __IO uint16_t I2SPR;
  594. uint16_t RESERVED8;
  595. __IO uint16_t HSCR;
  596. uint16_t RESERVED9;
  597. } SPI_TypeDef;
  598. /* TIM */
  599. typedef struct
  600. {
  601. __IO uint16_t CTLR1;
  602. uint16_t RESERVED0;
  603. __IO uint16_t CTLR2;
  604. uint16_t RESERVED1;
  605. __IO uint16_t SMCFGR;
  606. uint16_t RESERVED2;
  607. __IO uint16_t DMAINTENR;
  608. uint16_t RESERVED3;
  609. __IO uint16_t INTFR;
  610. uint16_t RESERVED4;
  611. __IO uint16_t SWEVGR;
  612. uint16_t RESERVED5;
  613. __IO uint16_t CHCTLR1;
  614. uint16_t RESERVED6;
  615. __IO uint16_t CHCTLR2;
  616. uint16_t RESERVED7;
  617. __IO uint16_t CCER;
  618. uint16_t RESERVED8;
  619. __IO uint16_t CNT;
  620. uint16_t RESERVED9;
  621. __IO uint16_t PSC;
  622. uint16_t RESERVED10;
  623. __IO uint16_t ATRLR;
  624. uint16_t RESERVED11;
  625. __IO uint16_t RPTCR;
  626. uint16_t RESERVED12;
  627. __IO uint16_t CH1CVR;
  628. uint16_t RESERVED13;
  629. __IO uint16_t CH2CVR;
  630. uint16_t RESERVED14;
  631. __IO uint16_t CH3CVR;
  632. uint16_t RESERVED15;
  633. __IO uint16_t CH4CVR;
  634. uint16_t RESERVED16;
  635. __IO uint16_t BDTR;
  636. uint16_t RESERVED17;
  637. __IO uint16_t DMACFGR;
  638. uint16_t RESERVED18;
  639. __IO uint16_t DMAADR;
  640. uint16_t RESERVED19;
  641. __IO uint16_t AUX;
  642. uint16_t RESERVED20;
  643. } TIM_TypeDef;
  644. /* Universal Synchronous Asynchronous Receiver Transmitter */
  645. typedef struct
  646. {
  647. __IO uint16_t STATR;
  648. uint16_t RESERVED0;
  649. __IO uint16_t DATAR;
  650. uint16_t RESERVED1;
  651. __IO uint16_t BRR;
  652. uint16_t RESERVED2;
  653. __IO uint16_t CTLR1;
  654. uint16_t RESERVED3;
  655. __IO uint16_t CTLR2;
  656. uint16_t RESERVED4;
  657. __IO uint16_t CTLR3;
  658. uint16_t RESERVED5;
  659. __IO uint16_t GPR;
  660. uint16_t RESERVED6;
  661. __IO uint16_t CTLR4;
  662. uint16_t RESERVED7;
  663. } USART_TypeDef;
  664. /* Window WatchDog */
  665. typedef struct
  666. {
  667. __IO uint32_t CTLR;
  668. __IO uint32_t CFGR;
  669. __IO uint32_t STATR;
  670. } WWDG_TypeDef;
  671. /* Enhanced Registers */
  672. typedef struct
  673. {
  674. __IO uint32_t EXTEN_CTR;
  675. uint32_t RESERVED0;
  676. __IO uint32_t EXTEN_CTR2;
  677. } EXTEN_TypeDef;
  678. /* OPA Registers */
  679. typedef struct
  680. {
  681. __IO uint32_t CR;
  682. } OPA_TypeDef;
  683. /* RNG Registers */
  684. typedef struct
  685. {
  686. __IO uint32_t CR;
  687. __IO uint32_t SR;
  688. __IO uint32_t DR;
  689. } RNG_TypeDef;
  690. /* DVP Registers */
  691. typedef struct
  692. {
  693. __IO uint8_t CR0;
  694. __IO uint8_t CR1;
  695. __IO uint8_t IER;
  696. __IO uint8_t Reserved0;
  697. __IO uint16_t ROW_NUM;
  698. __IO uint16_t COL_NUM;
  699. __IO uint32_t DMA_BUF0;
  700. __IO uint32_t DMA_BUF1;
  701. __IO uint8_t IFR;
  702. __IO uint8_t STATUS;
  703. __IO uint16_t Reserved1;
  704. __IO uint16_t ROW_CNT;
  705. __IO uint16_t Reserved2;
  706. __IO uint16_t HOFFCNT;
  707. __IO uint16_t VST;
  708. __IO uint16_t CAPCNT;
  709. __IO uint16_t VLINE;
  710. __IO uint32_t DR;
  711. } DVP_TypeDef;
  712. /* USBHS Registers */
  713. typedef struct
  714. {
  715. __IO uint8_t CONTROL;
  716. __IO uint8_t HOST_CTRL;
  717. __IO uint8_t INT_EN;
  718. __IO uint8_t DEV_AD;
  719. __IO uint16_t FRAME_NO;
  720. __IO uint8_t SUSPEND;
  721. __IO uint8_t RESERVED0;
  722. __IO uint8_t SPEED_TYPE;
  723. __IO uint8_t MIS_ST;
  724. __IO uint8_t INT_FG;
  725. __IO uint8_t INT_ST;
  726. __IO uint16_t RX_LEN;
  727. __IO uint16_t RESERVED1;
  728. __IO uint32_t ENDP_CONFIG;
  729. __IO uint32_t ENDP_TYPE;
  730. __IO uint32_t BUF_MODE;
  731. __IO uint32_t UEP0_DMA;
  732. __IO uint32_t UEP1_RX_DMA;
  733. __IO uint32_t UEP2_RX_DMA;
  734. __IO uint32_t UEP3_RX_DMA;
  735. __IO uint32_t UEP4_RX_DMA;
  736. __IO uint32_t UEP5_RX_DMA;
  737. __IO uint32_t UEP6_RX_DMA;
  738. __IO uint32_t UEP7_RX_DMA;
  739. __IO uint32_t UEP8_RX_DMA;
  740. __IO uint32_t UEP9_RX_DMA;
  741. __IO uint32_t UEP10_RX_DMA;
  742. __IO uint32_t UEP11_RX_DMA;
  743. __IO uint32_t UEP12_RX_DMA;
  744. __IO uint32_t UEP13_RX_DMA;
  745. __IO uint32_t UEP14_RX_DMA;
  746. __IO uint32_t UEP15_RX_DMA;
  747. __IO uint32_t UEP1_TX_DMA;
  748. __IO uint32_t UEP2_TX_DMA;
  749. __IO uint32_t UEP3_TX_DMA;
  750. __IO uint32_t UEP4_TX_DMA;
  751. __IO uint32_t UEP5_TX_DMA;
  752. __IO uint32_t UEP6_TX_DMA;
  753. __IO uint32_t UEP7_TX_DMA;
  754. __IO uint32_t UEP8_TX_DMA;
  755. __IO uint32_t UEP9_TX_DMA;
  756. __IO uint32_t UEP10_TX_DMA;
  757. __IO uint32_t UEP11_TX_DMA;
  758. __IO uint32_t UEP12_TX_DMA;
  759. __IO uint32_t UEP13_TX_DMA;
  760. __IO uint32_t UEP14_TX_DMA;
  761. __IO uint32_t UEP15_TX_DMA;
  762. __IO uint16_t UEP0_MAX_LEN;
  763. __IO uint16_t RESERVED2;
  764. __IO uint16_t UEP1_MAX_LEN;
  765. __IO uint16_t RESERVED3;
  766. __IO uint16_t UEP2_MAX_LEN;
  767. __IO uint16_t RESERVED4;
  768. __IO uint16_t UEP3_MAX_LEN;
  769. __IO uint16_t RESERVED5;
  770. __IO uint16_t UEP4_MAX_LEN;
  771. __IO uint16_t RESERVED6;
  772. __IO uint16_t UEP5_MAX_LEN;
  773. __IO uint16_t RESERVED7;
  774. __IO uint16_t UEP6_MAX_LEN;
  775. __IO uint16_t RESERVED8;
  776. __IO uint16_t UEP7_MAX_LEN;
  777. __IO uint16_t RESERVED9;
  778. __IO uint16_t UEP8_MAX_LEN;
  779. __IO uint16_t RESERVED10;
  780. __IO uint16_t UEP9_MAX_LEN;
  781. __IO uint16_t RESERVED11;
  782. __IO uint16_t UEP10_MAX_LEN;
  783. __IO uint16_t RESERVED12;
  784. __IO uint16_t UEP11_MAX_LEN;
  785. __IO uint16_t RESERVED13;
  786. __IO uint16_t UEP12_MAX_LEN;
  787. __IO uint16_t RESERVED14;
  788. __IO uint16_t UEP13_MAX_LEN;
  789. __IO uint16_t RESERVED15;
  790. __IO uint16_t UEP14_MAX_LEN;
  791. __IO uint16_t RESERVED16;
  792. __IO uint16_t UEP15_MAX_LEN;
  793. __IO uint16_t RESERVED17;
  794. __IO uint16_t UEP0_TX_LEN;
  795. __IO uint8_t UEP0_TX_CTRL;
  796. __IO uint8_t UEP0_RX_CTRL;
  797. __IO uint16_t UEP1_TX_LEN;
  798. __IO uint8_t UEP1_TX_CTRL;
  799. __IO uint8_t UEP1_RX_CTRL;
  800. __IO uint16_t UEP2_TX_LEN;
  801. __IO uint8_t UEP2_TX_CTRL;
  802. __IO uint8_t UEP2_RX_CTRL;
  803. __IO uint16_t UEP3_TX_LEN;
  804. __IO uint8_t UEP3_TX_CTRL;
  805. __IO uint8_t UEP3_RX_CTRL;
  806. __IO uint16_t UEP4_TX_LEN;
  807. __IO uint8_t UEP4_TX_CTRL;
  808. __IO uint8_t UEP4_RX_CTRL;
  809. __IO uint16_t UEP5_TX_LEN;
  810. __IO uint8_t UEP5_TX_CTRL;
  811. __IO uint8_t UEP5_RX_CTRL;
  812. __IO uint16_t UEP6_TX_LEN;
  813. __IO uint8_t UEP6_TX_CTRL;
  814. __IO uint8_t UEP6_RX_CTRL;
  815. __IO uint16_t UEP7_TX_LEN;
  816. __IO uint8_t UEP7_TX_CTRL;
  817. __IO uint8_t UEP7_RX_CTRL;
  818. __IO uint16_t UEP8_TX_LEN;
  819. __IO uint8_t UEP8_TX_CTRL;
  820. __IO uint8_t UEP8_RX_CTRL;
  821. __IO uint16_t UEP9_TX_LEN;
  822. __IO uint8_t UEP9_TX_CTRL;
  823. __IO uint8_t UEP9_RX_CTRL;
  824. __IO uint16_t UEP10_TX_LEN;
  825. __IO uint8_t UEP10_TX_CTRL;
  826. __IO uint8_t UEP10_RX_CTRL;
  827. __IO uint16_t UEP11_TX_LEN;
  828. __IO uint8_t UEP11_TX_CTRL;
  829. __IO uint8_t UEP11_RX_CTRL;
  830. __IO uint16_t UEP12_TX_LEN;
  831. __IO uint8_t UEP12_TX_CTRL;
  832. __IO uint8_t UEP12_RX_CTRL;
  833. __IO uint16_t UEP13_TX_LEN;
  834. __IO uint8_t UEP13_TX_CTRL;
  835. __IO uint8_t UEP13_RX_CTRL;
  836. __IO uint16_t UEP14_TX_LEN;
  837. __IO uint8_t UEP14_TX_CTRL;
  838. __IO uint8_t UEP14_RX_CTRL;
  839. __IO uint16_t UEP15_TX_LEN;
  840. __IO uint8_t UEP15_TX_CTRL;
  841. __IO uint8_t UEP15_RX_CTRL;
  842. } USBHSD_TypeDef;
  843. typedef struct __attribute__((packed))
  844. {
  845. __IO uint8_t CONTROL;
  846. __IO uint8_t HOST_CTRL;
  847. __IO uint8_t INT_EN;
  848. __IO uint8_t DEV_AD;
  849. __IO uint16_t FRAME_NO;
  850. __IO uint8_t SUSPEND;
  851. __IO uint8_t RESERVED0;
  852. __IO uint8_t SPEED_TYPE;
  853. __IO uint8_t MIS_ST;
  854. __IO uint8_t INT_FG;
  855. __IO uint8_t INT_ST;
  856. __IO uint16_t RX_LEN;
  857. __IO uint16_t RESERVED1;
  858. __IO uint32_t HOST_EP_CONFIG;
  859. __IO uint32_t HOST_EP_TYPE;
  860. __IO uint32_t RESERVED2;
  861. __IO uint32_t RESERVED3;
  862. __IO uint32_t RESERVED4;
  863. __IO uint32_t HOST_RX_DMA;
  864. __IO uint32_t RESERVED5;
  865. __IO uint32_t RESERVED6;
  866. __IO uint32_t RESERVED7;
  867. __IO uint32_t RESERVED8;
  868. __IO uint32_t RESERVED9;
  869. __IO uint32_t RESERVED10;
  870. __IO uint32_t RESERVED11;
  871. __IO uint32_t RESERVED12;
  872. __IO uint32_t RESERVED13;
  873. __IO uint32_t RESERVED14;
  874. __IO uint32_t RESERVED15;
  875. __IO uint32_t RESERVED16;
  876. __IO uint32_t RESERVED17;
  877. __IO uint32_t RESERVED18;
  878. __IO uint32_t RESERVED19;
  879. __IO uint32_t HOST_TX_DMA;
  880. __IO uint32_t RESERVED20;
  881. __IO uint32_t RESERVED21;
  882. __IO uint32_t RESERVED22;
  883. __IO uint32_t RESERVED23;
  884. __IO uint32_t RESERVED24;
  885. __IO uint32_t RESERVED25;
  886. __IO uint32_t RESERVED26;
  887. __IO uint32_t RESERVED27;
  888. __IO uint32_t RESERVED28;
  889. __IO uint32_t RESERVED29;
  890. __IO uint32_t RESERVED30;
  891. __IO uint32_t RESERVED31;
  892. __IO uint32_t RESERVED32;
  893. __IO uint32_t RESERVED33;
  894. __IO uint16_t HOST_RX_MAX_LEN;
  895. __IO uint16_t RESERVED34;
  896. __IO uint32_t RESERVED35;
  897. __IO uint32_t RESERVED36;
  898. __IO uint32_t RESERVED37;
  899. __IO uint32_t RESERVED38;
  900. __IO uint32_t RESERVED39;
  901. __IO uint32_t RESERVED40;
  902. __IO uint32_t RESERVED41;
  903. __IO uint32_t RESERVED42;
  904. __IO uint32_t RESERVED43;
  905. __IO uint32_t RESERVED44;
  906. __IO uint32_t RESERVED45;
  907. __IO uint32_t RESERVED46;
  908. __IO uint32_t RESERVED47;
  909. __IO uint32_t RESERVED48;
  910. __IO uint32_t RESERVED49;
  911. __IO uint8_t HOST_EP_PID;
  912. __IO uint8_t RESERVED50;
  913. __IO uint8_t RESERVED51;
  914. __IO uint8_t HOST_RX_CTRL;
  915. __IO uint16_t HOST_TX_LEN;
  916. __IO uint8_t HOST_TX_CTRL;
  917. __IO uint8_t RESERVED52;
  918. __IO uint16_t HOST_SPLIT_DATA;
  919. } USBHSH_TypeDef;
  920. /* USBOTG_FS Registers */
  921. typedef struct
  922. {
  923. __IO uint8_t BASE_CTRL;
  924. __IO uint8_t UDEV_CTRL;
  925. __IO uint8_t INT_EN;
  926. __IO uint8_t DEV_ADDR;
  927. __IO uint8_t Reserve0;
  928. __IO uint8_t MIS_ST;
  929. __IO uint8_t INT_FG;
  930. __IO uint8_t INT_ST;
  931. __IO uint16_t RX_LEN;
  932. __IO uint16_t Reserve1;
  933. __IO uint8_t UEP4_1_MOD;
  934. __IO uint8_t UEP2_3_MOD;
  935. __IO uint8_t UEP5_6_MOD;
  936. __IO uint8_t UEP7_MOD;
  937. __IO uint32_t UEP0_DMA;
  938. __IO uint32_t UEP1_DMA;
  939. __IO uint32_t UEP2_DMA;
  940. __IO uint32_t UEP3_DMA;
  941. __IO uint32_t UEP4_DMA;
  942. __IO uint32_t UEP5_DMA;
  943. __IO uint32_t UEP6_DMA;
  944. __IO uint32_t UEP7_DMA;
  945. __IO uint16_t UEP0_TX_LEN;
  946. __IO uint8_t UEP0_TX_CTRL;
  947. __IO uint8_t UEP0_RX_CTRL;
  948. __IO uint16_t UEP1_TX_LEN;
  949. __IO uint8_t UEP1_TX_CTRL;
  950. __IO uint8_t UEP1_RX_CTRL;
  951. __IO uint16_t UEP2_TX_LEN;
  952. __IO uint8_t UEP2_TX_CTRL;
  953. __IO uint8_t UEP2_RX_CTRL;
  954. __IO uint16_t UEP3_TX_LEN;
  955. __IO uint8_t UEP3_TX_CTRL;
  956. __IO uint8_t UEP3_RX_CTRL;
  957. __IO uint16_t UEP4_TX_LEN;
  958. __IO uint8_t UEP4_TX_CTRL;
  959. __IO uint8_t UEP4_RX_CTRL;
  960. __IO uint16_t UEP5_TX_LEN;
  961. __IO uint8_t UEP5_TX_CTRL;
  962. __IO uint8_t UEP5_RX_CTRL;
  963. __IO uint16_t UEP6_TX_LEN;
  964. __IO uint8_t UEP6_TX_CTRL;
  965. __IO uint8_t UEP6_RX_CTRL;
  966. __IO uint16_t UEP7_TX_LEN;
  967. __IO uint8_t UEP7_TX_CTRL;
  968. __IO uint8_t UEP7_RX_CTRL;
  969. __IO uint32_t Reserve2;
  970. __IO uint32_t OTG_CR;
  971. __IO uint32_t OTG_SR;
  972. }USBFSD_TypeDef;
  973. typedef struct __attribute__((packed))
  974. {
  975. __IO uint8_t BASE_CTRL;
  976. __IO uint8_t HOST_CTRL;
  977. __IO uint8_t INT_EN;
  978. __IO uint8_t DEV_ADDR;
  979. __IO uint8_t Reserve0;
  980. __IO uint8_t MIS_ST;
  981. __IO uint8_t INT_FG;
  982. __IO uint8_t INT_ST;
  983. __IO uint16_t RX_LEN;
  984. __IO uint16_t Reserve1;
  985. __IO uint8_t Reserve2;
  986. __IO uint8_t HOST_EP_MOD;
  987. __IO uint16_t Reserve3;
  988. __IO uint32_t Reserve4;
  989. __IO uint32_t Reserve5;
  990. __IO uint32_t HOST_RX_DMA;
  991. __IO uint32_t HOST_TX_DMA;
  992. __IO uint32_t Reserve6;
  993. __IO uint32_t Reserve7;
  994. __IO uint32_t Reserve8;
  995. __IO uint32_t Reserve9;
  996. __IO uint32_t Reserve10;
  997. __IO uint16_t Reserve11;
  998. __IO uint16_t HOST_SETUP;
  999. __IO uint8_t HOST_EP_PID;
  1000. __IO uint8_t Reserve12;
  1001. __IO uint8_t Reserve13;
  1002. __IO uint8_t HOST_RX_CTRL;
  1003. __IO uint16_t HOST_TX_LEN;
  1004. __IO uint8_t HOST_TX_CTRL;
  1005. __IO uint8_t Reserve14;
  1006. __IO uint32_t Reserve15;
  1007. __IO uint32_t Reserve16;
  1008. __IO uint32_t Reserve17;
  1009. __IO uint32_t Reserve18;
  1010. __IO uint32_t Reserve19;
  1011. __IO uint32_t OTG_CR;
  1012. __IO uint32_t OTG_SR;
  1013. }USBFSH_TypeDef;
  1014. /* Ethernet MAC */
  1015. typedef struct
  1016. {
  1017. __IO uint32_t MACCR;
  1018. __IO uint32_t MACFFR;
  1019. __IO uint32_t MACHTHR;
  1020. __IO uint32_t MACHTLR;
  1021. __IO uint32_t MACMIIAR;
  1022. __IO uint32_t MACMIIDR;
  1023. __IO uint32_t MACFCR;
  1024. __IO uint32_t MACVLANTR;
  1025. uint32_t RESERVED0[2];
  1026. __IO uint32_t MACRWUFFR;
  1027. __IO uint32_t MACPMTCSR;
  1028. uint32_t RESERVED1[2];
  1029. __IO uint32_t MACSR;
  1030. __IO uint32_t MACIMR;
  1031. __IO uint32_t MACA0HR;
  1032. __IO uint32_t MACA0LR;
  1033. __IO uint32_t MACA1HR;
  1034. __IO uint32_t MACA1LR;
  1035. __IO uint32_t MACA2HR;
  1036. __IO uint32_t MACA2LR;
  1037. __IO uint32_t MACA3HR;
  1038. __IO uint32_t MACA3LR;
  1039. uint32_t RESERVED2[14];
  1040. __IO uint32_t MACCFG0;
  1041. uint32_t RESERVED10[25];
  1042. __IO uint32_t MMCCR;
  1043. __IO uint32_t MMCRIR;
  1044. __IO uint32_t MMCTIR;
  1045. __IO uint32_t MMCRIMR;
  1046. __IO uint32_t MMCTIMR;
  1047. uint32_t RESERVED3[14];
  1048. __IO uint32_t MMCTGFSCCR;
  1049. __IO uint32_t MMCTGFMSCCR;
  1050. uint32_t RESERVED4[5];
  1051. __IO uint32_t MMCTGFCR;
  1052. uint32_t RESERVED5[10];
  1053. __IO uint32_t MMCRFCECR;
  1054. __IO uint32_t MMCRFAECR;
  1055. uint32_t RESERVED6[10];
  1056. __IO uint32_t MMCRGUFCR;
  1057. uint32_t RESERVED7[334];
  1058. __IO uint32_t PTPTSCR;
  1059. __IO uint32_t PTPSSIR;
  1060. __IO uint32_t PTPTSHR;
  1061. __IO uint32_t PTPTSLR;
  1062. __IO uint32_t PTPTSHUR;
  1063. __IO uint32_t PTPTSLUR;
  1064. __IO uint32_t PTPTSAR;
  1065. __IO uint32_t PTPTTHR;
  1066. __IO uint32_t PTPTTLR;
  1067. uint32_t RESERVED8[567];
  1068. __IO uint32_t DMABMR;
  1069. __IO uint32_t DMATPDR;
  1070. __IO uint32_t DMARPDR;
  1071. __IO uint32_t DMARDLAR;
  1072. __IO uint32_t DMATDLAR;
  1073. __IO uint32_t DMASR;
  1074. __IO uint32_t DMAOMR;
  1075. __IO uint32_t DMAIER;
  1076. __IO uint32_t DMAMFBOCR;
  1077. uint32_t RESERVED9[9];
  1078. __IO uint32_t DMACHTDR;
  1079. __IO uint32_t DMACHRDR;
  1080. __IO uint32_t DMACHTBAR;
  1081. __IO uint32_t DMACHRBAR;
  1082. } ETH_TypeDef;
  1083. /* Peripheral memory map */
  1084. #define FLASH_BASE ((uint32_t)0x08000000) /* FLASH base address in the alias region */
  1085. #define SRAM_BASE ((uint32_t)0x20000000) /* SRAM base address in the alias region */
  1086. #define PERIPH_BASE ((uint32_t)0x40000000) /* Peripheral base address in the alias region */
  1087. #define FSMC_R_BASE ((uint32_t)0xA0000000) /* FSMC registers base address */
  1088. #define APB1PERIPH_BASE (PERIPH_BASE)
  1089. #define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
  1090. #define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
  1091. #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
  1092. #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
  1093. #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
  1094. #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
  1095. #define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
  1096. #define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
  1097. #define UART6_BASE (APB1PERIPH_BASE + 0x1800)
  1098. #define UART7_BASE (APB1PERIPH_BASE + 0x1C00)
  1099. #define UART8_BASE (APB1PERIPH_BASE + 0x2000)
  1100. #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
  1101. #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
  1102. #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
  1103. #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
  1104. #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
  1105. #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
  1106. #define USART3_BASE (APB1PERIPH_BASE + 0x4800)
  1107. #define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
  1108. #define UART5_BASE (APB1PERIPH_BASE + 0x5000)
  1109. #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
  1110. #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
  1111. #define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
  1112. #define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
  1113. #define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
  1114. #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
  1115. #define DAC_BASE (APB1PERIPH_BASE + 0x7400)
  1116. #define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
  1117. #define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
  1118. #define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
  1119. #define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
  1120. #define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
  1121. #define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
  1122. #define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
  1123. #define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
  1124. #define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
  1125. #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
  1126. #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
  1127. #define TIM8_BASE (APB2PERIPH_BASE + 0x3400)
  1128. #define USART1_BASE (APB2PERIPH_BASE + 0x3800)
  1129. #define ADC3_BASE (APB2PERIPH_BASE + 0x3C00)
  1130. #define TIM9_BASE (APB2PERIPH_BASE + 0x4C00)
  1131. #define TIM10_BASE (APB2PERIPH_BASE + 0x5000)
  1132. #define SDIO_BASE (APB2PERIPH_BASE + 0x8000)
  1133. #define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
  1134. #define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
  1135. #define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
  1136. #define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
  1137. #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
  1138. #define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
  1139. #define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
  1140. #define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
  1141. #define DMA2_BASE (AHBPERIPH_BASE + 0x0400)
  1142. #define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)
  1143. #define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)
  1144. #define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)
  1145. #define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)
  1146. #define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)
  1147. #define DMA2_Channel6_BASE (AHBPERIPH_BASE + 0x046C)
  1148. #define DMA2_Channel7_BASE (AHBPERIPH_BASE + 0x0480)
  1149. #define DMA2_Channel8_BASE (AHBPERIPH_BASE + 0x0490)
  1150. #define DMA2_Channel9_BASE (AHBPERIPH_BASE + 0x04A0)
  1151. #define DMA2_Channel10_BASE (AHBPERIPH_BASE + 0x04B0)
  1152. #define DMA2_Channel11_BASE (AHBPERIPH_BASE + 0x04C0)
  1153. #define DMA2_EXTEN_BASE (AHBPERIPH_BASE + 0x04D0)
  1154. #define RCC_BASE (AHBPERIPH_BASE + 0x1000)
  1155. #define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000)
  1156. #define CRC_BASE (AHBPERIPH_BASE + 0x3000)
  1157. #define USBHS_BASE (AHBPERIPH_BASE + 0x3400)
  1158. #define EXTEN_BASE (AHBPERIPH_BASE + 0x3800)
  1159. #define OPA_BASE (AHBPERIPH_BASE + 0x3804)
  1160. #define RNG_BASE (AHBPERIPH_BASE + 0x3C00)
  1161. #define ETH_BASE (AHBPERIPH_BASE + 0x8000)
  1162. #define ETH_MAC_BASE (ETH_BASE)
  1163. #define ETH_MMC_BASE (ETH_BASE + 0x0100)
  1164. #define ETH_PTP_BASE (ETH_BASE + 0x0700)
  1165. #define ETH_DMA_BASE (ETH_BASE + 0x1000)
  1166. #define USBFS_BASE ((uint32_t)0x50000000)
  1167. #define DVP_BASE ((uint32_t)0x50050000)
  1168. #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
  1169. #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
  1170. #define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060)
  1171. #define OB_BASE ((uint32_t)0x1FFFF800)
  1172. #define FEATURE_SIGN ((uint32_t)0x1FFFF7D0)
  1173. /* Peripheral declaration */
  1174. #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
  1175. #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
  1176. #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
  1177. #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
  1178. #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
  1179. #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
  1180. #define UART6 ((USART_TypeDef *) UART6_BASE)
  1181. #define UART7 ((USART_TypeDef *) UART7_BASE)
  1182. #define UART8 ((USART_TypeDef *) UART8_BASE)
  1183. #define RTC ((RTC_TypeDef *) RTC_BASE)
  1184. #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
  1185. #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
  1186. #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
  1187. #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
  1188. #define USART2 ((USART_TypeDef *) USART2_BASE)
  1189. #define USART3 ((USART_TypeDef *) USART3_BASE)
  1190. #define UART4 ((USART_TypeDef *) UART4_BASE)
  1191. #define UART5 ((USART_TypeDef *) UART5_BASE)
  1192. #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
  1193. #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
  1194. #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
  1195. #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
  1196. #define BKP ((BKP_TypeDef *) BKP_BASE)
  1197. #define PWR ((PWR_TypeDef *) PWR_BASE)
  1198. #define DAC ((DAC_TypeDef *) DAC_BASE)
  1199. #define AFIO ((AFIO_TypeDef *) AFIO_BASE)
  1200. #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
  1201. #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
  1202. #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
  1203. #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
  1204. #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
  1205. #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
  1206. #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
  1207. #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
  1208. #define TKey1 ((ADC_TypeDef *) ADC1_BASE)
  1209. #define TKey2 ((ADC_TypeDef *) ADC2_BASE)
  1210. #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
  1211. #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
  1212. #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
  1213. #define USART1 ((USART_TypeDef *) USART1_BASE)
  1214. #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
  1215. #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
  1216. #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
  1217. #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
  1218. #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
  1219. #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
  1220. #define DMA2_EXTEN ((DMA_TypeDef *) DMA2_EXTEN_BASE)
  1221. #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
  1222. #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
  1223. #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
  1224. #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
  1225. #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
  1226. #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
  1227. #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
  1228. #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
  1229. #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
  1230. #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
  1231. #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
  1232. #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
  1233. #define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
  1234. #define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
  1235. #define DMA2_Channel8 ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE)
  1236. #define DMA2_Channel9 ((DMA_Channel_TypeDef *) DMA2_Channel9_BASE)
  1237. #define DMA2_Channel10 ((DMA_Channel_TypeDef *) DMA2_Channel10_BASE)
  1238. #define DMA2_Channel11 ((DMA_Channel_TypeDef *) DMA2_Channel11_BASE)
  1239. #define RCC ((RCC_TypeDef *) RCC_BASE)
  1240. #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
  1241. #define CRC ((CRC_TypeDef *) CRC_BASE)
  1242. #define USBHSD ((USBHSD_TypeDef *) USBHS_BASE)
  1243. #define USBHSH ((USBHSH_TypeDef *) USBHS_BASE)
  1244. #define USBFSD ((USBFSD_TypeDef *)USBFS_BASE)
  1245. #define USBFSH ((USBFSH_TypeDef *)USBFS_BASE)
  1246. #define EXTEN ((EXTEN_TypeDef *) EXTEN_BASE)
  1247. #define OPA ((OPA_TypeDef *) OPA_BASE)
  1248. #define RNG ((RNG_TypeDef *) RNG_BASE)
  1249. #define ETH ((ETH_TypeDef *) ETH_BASE)
  1250. #define DVP ((DVP_TypeDef *) DVP_BASE)
  1251. #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
  1252. #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
  1253. #define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
  1254. #define OB ((OB_TypeDef *) OB_BASE)
  1255. /******************************************************************************/
  1256. /* Peripheral Registers Bits Definition */
  1257. /******************************************************************************/
  1258. /******************************************************************************/
  1259. /* Analog to Digital Converter */
  1260. /******************************************************************************/
  1261. /******************** Bit definition for ADC_STATR register ********************/
  1262. #define ADC_AWD ((uint8_t)0x01) /* Analog watchdog flag */
  1263. #define ADC_EOC ((uint8_t)0x02) /* End of conversion */
  1264. #define ADC_JEOC ((uint8_t)0x04) /* Injected channel end of conversion */
  1265. #define ADC_JSTRT ((uint8_t)0x08) /* Injected channel Start flag */
  1266. #define ADC_STRT ((uint8_t)0x10) /* Regular channel Start flag */
  1267. /******************* Bit definition for ADC_CTLR1 register ********************/
  1268. #define ADC_AWDCH ((uint32_t)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */
  1269. #define ADC_AWDCH_0 ((uint32_t)0x00000001) /* Bit 0 */
  1270. #define ADC_AWDCH_1 ((uint32_t)0x00000002) /* Bit 1 */
  1271. #define ADC_AWDCH_2 ((uint32_t)0x00000004) /* Bit 2 */
  1272. #define ADC_AWDCH_3 ((uint32_t)0x00000008) /* Bit 3 */
  1273. #define ADC_AWDCH_4 ((uint32_t)0x00000010) /* Bit 4 */
  1274. #define ADC_EOCIE ((uint32_t)0x00000020) /* Interrupt enable for EOC */
  1275. #define ADC_AWDIE ((uint32_t)0x00000040) /* Analog Watchdog interrupt enable */
  1276. #define ADC_JEOCIE ((uint32_t)0x00000080) /* Interrupt enable for injected channels */
  1277. #define ADC_SCAN ((uint32_t)0x00000100) /* Scan mode */
  1278. #define ADC_AWDSGL ((uint32_t)0x00000200) /* Enable the watchdog on a single channel in scan mode */
  1279. #define ADC_JAUTO ((uint32_t)0x00000400) /* Automatic injected group conversion */
  1280. #define ADC_DISCEN ((uint32_t)0x00000800) /* Discontinuous mode on regular channels */
  1281. #define ADC_JDISCEN ((uint32_t)0x00001000) /* Discontinuous mode on injected channels */
  1282. #define ADC_DISCNUM ((uint32_t)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */
  1283. #define ADC_DISCNUM_0 ((uint32_t)0x00002000) /* Bit 0 */
  1284. #define ADC_DISCNUM_1 ((uint32_t)0x00004000) /* Bit 1 */
  1285. #define ADC_DISCNUM_2 ((uint32_t)0x00008000) /* Bit 2 */
  1286. #define ADC_DUALMOD ((uint32_t)0x000F0000) /* DUALMOD[3:0] bits (Dual mode selection) */
  1287. #define ADC_DUALMOD_0 ((uint32_t)0x00010000) /* Bit 0 */
  1288. #define ADC_DUALMOD_1 ((uint32_t)0x00020000) /* Bit 1 */
  1289. #define ADC_DUALMOD_2 ((uint32_t)0x00040000) /* Bit 2 */
  1290. #define ADC_DUALMOD_3 ((uint32_t)0x00080000) /* Bit 3 */
  1291. #define ADC_JAWDEN ((uint32_t)0x00400000) /* Analog watchdog enable on injected channels */
  1292. #define ADC_AWDEN ((uint32_t)0x00800000) /* Analog watchdog enable on regular channels */
  1293. #define ADC_TKENABLE ((uint32_t)0x01000000) /*TKEY enable*/
  1294. #define ADC_TKITUNE ((uint32_t)0x02000000)
  1295. #define ADC_BUFEN ((uint32_t)0x04000000)
  1296. #define ADC_PGA ((uint32_t)0x18000000)
  1297. #define ADC_PGA_0 ((uint32_t)0x08000000)
  1298. #define ADC_PGA_1 ((uint32_t)0x10000000)
  1299. /******************* Bit definition for ADC_CTLR2 register ********************/
  1300. #define ADC_ADON ((uint32_t)0x00000001) /* A/D Converter ON / OFF */
  1301. #define ADC_CONT ((uint32_t)0x00000002) /* Continuous Conversion */
  1302. #define ADC_CAL ((uint32_t)0x00000004) /* A/D Calibration */
  1303. #define ADC_RSTCAL ((uint32_t)0x00000008) /* Reset Calibration */
  1304. #define ADC_DMA ((uint32_t)0x00000100) /* Direct Memory access mode */
  1305. #define ADC_ALIGN ((uint32_t)0x00000800) /* Data Alignment */
  1306. #define ADC_JEXTSEL ((uint32_t)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */
  1307. #define ADC_JEXTSEL_0 ((uint32_t)0x00001000) /* Bit 0 */
  1308. #define ADC_JEXTSEL_1 ((uint32_t)0x00002000) /* Bit 1 */
  1309. #define ADC_JEXTSEL_2 ((uint32_t)0x00004000) /* Bit 2 */
  1310. #define ADC_JEXTTRIG ((uint32_t)0x00008000) /* External Trigger Conversion mode for injected channels */
  1311. #define ADC_EXTSEL ((uint32_t)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */
  1312. #define ADC_EXTSEL_0 ((uint32_t)0x00020000) /* Bit 0 */
  1313. #define ADC_EXTSEL_1 ((uint32_t)0x00040000) /* Bit 1 */
  1314. #define ADC_EXTSEL_2 ((uint32_t)0x00080000) /* Bit 2 */
  1315. #define ADC_EXTTRIG ((uint32_t)0x00100000) /* External Trigger Conversion mode for regular channels */
  1316. #define ADC_JSWSTART ((uint32_t)0x00200000) /* Start Conversion of injected channels */
  1317. #define ADC_SWSTART ((uint32_t)0x00400000) /* Start Conversion of regular channels */
  1318. #define ADC_TSVREFE ((uint32_t)0x00800000) /* Temperature Sensor and VREFINT Enable */
  1319. /****************** Bit definition for ADC_SAMPTR1 register *******************/
  1320. #define ADC_SMP10 ((uint32_t)0x00000007) /* SMP10[2:0] bits (Channel 10 Sample time selection) */
  1321. #define ADC_SMP10_0 ((uint32_t)0x00000001) /* Bit 0 */
  1322. #define ADC_SMP10_1 ((uint32_t)0x00000002) /* Bit 1 */
  1323. #define ADC_SMP10_2 ((uint32_t)0x00000004) /* Bit 2 */
  1324. #define ADC_SMP11 ((uint32_t)0x00000038) /* SMP11[2:0] bits (Channel 11 Sample time selection) */
  1325. #define ADC_SMP11_0 ((uint32_t)0x00000008) /* Bit 0 */
  1326. #define ADC_SMP11_1 ((uint32_t)0x00000010) /* Bit 1 */
  1327. #define ADC_SMP11_2 ((uint32_t)0x00000020) /* Bit 2 */
  1328. #define ADC_SMP12 ((uint32_t)0x000001C0) /* SMP12[2:0] bits (Channel 12 Sample time selection) */
  1329. #define ADC_SMP12_0 ((uint32_t)0x00000040) /* Bit 0 */
  1330. #define ADC_SMP12_1 ((uint32_t)0x00000080) /* Bit 1 */
  1331. #define ADC_SMP12_2 ((uint32_t)0x00000100) /* Bit 2 */
  1332. #define ADC_SMP13 ((uint32_t)0x00000E00) /* SMP13[2:0] bits (Channel 13 Sample time selection) */
  1333. #define ADC_SMP13_0 ((uint32_t)0x00000200) /* Bit 0 */
  1334. #define ADC_SMP13_1 ((uint32_t)0x00000400) /* Bit 1 */
  1335. #define ADC_SMP13_2 ((uint32_t)0x00000800) /* Bit 2 */
  1336. #define ADC_SMP14 ((uint32_t)0x00007000) /* SMP14[2:0] bits (Channel 14 Sample time selection) */
  1337. #define ADC_SMP14_0 ((uint32_t)0x00001000) /* Bit 0 */
  1338. #define ADC_SMP14_1 ((uint32_t)0x00002000) /* Bit 1 */
  1339. #define ADC_SMP14_2 ((uint32_t)0x00004000) /* Bit 2 */
  1340. #define ADC_SMP15 ((uint32_t)0x00038000) /* SMP15[2:0] bits (Channel 15 Sample time selection) */
  1341. #define ADC_SMP15_0 ((uint32_t)0x00008000) /* Bit 0 */
  1342. #define ADC_SMP15_1 ((uint32_t)0x00010000) /* Bit 1 */
  1343. #define ADC_SMP15_2 ((uint32_t)0x00020000) /* Bit 2 */
  1344. #define ADC_SMP16 ((uint32_t)0x001C0000) /* SMP16[2:0] bits (Channel 16 Sample time selection) */
  1345. #define ADC_SMP16_0 ((uint32_t)0x00040000) /* Bit 0 */
  1346. #define ADC_SMP16_1 ((uint32_t)0x00080000) /* Bit 1 */
  1347. #define ADC_SMP16_2 ((uint32_t)0x00100000) /* Bit 2 */
  1348. #define ADC_SMP17 ((uint32_t)0x00E00000) /* SMP17[2:0] bits (Channel 17 Sample time selection) */
  1349. #define ADC_SMP17_0 ((uint32_t)0x00200000) /* Bit 0 */
  1350. #define ADC_SMP17_1 ((uint32_t)0x00400000) /* Bit 1 */
  1351. #define ADC_SMP17_2 ((uint32_t)0x00800000) /* Bit 2 */
  1352. /****************** Bit definition for ADC_SAMPTR2 register *******************/
  1353. #define ADC_SMP0 ((uint32_t)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */
  1354. #define ADC_SMP0_0 ((uint32_t)0x00000001) /* Bit 0 */
  1355. #define ADC_SMP0_1 ((uint32_t)0x00000002) /* Bit 1 */
  1356. #define ADC_SMP0_2 ((uint32_t)0x00000004) /* Bit 2 */
  1357. #define ADC_SMP1 ((uint32_t)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */
  1358. #define ADC_SMP1_0 ((uint32_t)0x00000008) /* Bit 0 */
  1359. #define ADC_SMP1_1 ((uint32_t)0x00000010) /* Bit 1 */
  1360. #define ADC_SMP1_2 ((uint32_t)0x00000020) /* Bit 2 */
  1361. #define ADC_SMP2 ((uint32_t)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */
  1362. #define ADC_SMP2_0 ((uint32_t)0x00000040) /* Bit 0 */
  1363. #define ADC_SMP2_1 ((uint32_t)0x00000080) /* Bit 1 */
  1364. #define ADC_SMP2_2 ((uint32_t)0x00000100) /* Bit 2 */
  1365. #define ADC_SMP3 ((uint32_t)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */
  1366. #define ADC_SMP3_0 ((uint32_t)0x00000200) /* Bit 0 */
  1367. #define ADC_SMP3_1 ((uint32_t)0x00000400) /* Bit 1 */
  1368. #define ADC_SMP3_2 ((uint32_t)0x00000800) /* Bit 2 */
  1369. #define ADC_SMP4 ((uint32_t)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */
  1370. #define ADC_SMP4_0 ((uint32_t)0x00001000) /* Bit 0 */
  1371. #define ADC_SMP4_1 ((uint32_t)0x00002000) /* Bit 1 */
  1372. #define ADC_SMP4_2 ((uint32_t)0x00004000) /* Bit 2 */
  1373. #define ADC_SMP5 ((uint32_t)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */
  1374. #define ADC_SMP5_0 ((uint32_t)0x00008000) /* Bit 0 */
  1375. #define ADC_SMP5_1 ((uint32_t)0x00010000) /* Bit 1 */
  1376. #define ADC_SMP5_2 ((uint32_t)0x00020000) /* Bit 2 */
  1377. #define ADC_SMP6 ((uint32_t)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */
  1378. #define ADC_SMP6_0 ((uint32_t)0x00040000) /* Bit 0 */
  1379. #define ADC_SMP6_1 ((uint32_t)0x00080000) /* Bit 1 */
  1380. #define ADC_SMP6_2 ((uint32_t)0x00100000) /* Bit 2 */
  1381. #define ADC_SMP7 ((uint32_t)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */
  1382. #define ADC_SMP7_0 ((uint32_t)0x00200000) /* Bit 0 */
  1383. #define ADC_SMP7_1 ((uint32_t)0x00400000) /* Bit 1 */
  1384. #define ADC_SMP7_2 ((uint32_t)0x00800000) /* Bit 2 */
  1385. #define ADC_SMP8 ((uint32_t)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */
  1386. #define ADC_SMP8_0 ((uint32_t)0x01000000) /* Bit 0 */
  1387. #define ADC_SMP8_1 ((uint32_t)0x02000000) /* Bit 1 */
  1388. #define ADC_SMP8_2 ((uint32_t)0x04000000) /* Bit 2 */
  1389. #define ADC_SMP9 ((uint32_t)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */
  1390. #define ADC_SMP9_0 ((uint32_t)0x08000000) /* Bit 0 */
  1391. #define ADC_SMP9_1 ((uint32_t)0x10000000) /* Bit 1 */
  1392. #define ADC_SMP9_2 ((uint32_t)0x20000000) /* Bit 2 */
  1393. /****************** Bit definition for ADC_IOFR1 register *******************/
  1394. #define ADC_JOFFSET1 ((uint16_t)0x0FFF) /* Data offset for injected channel 1 */
  1395. /****************** Bit definition for ADC_IOFR2 register *******************/
  1396. #define ADC_JOFFSET2 ((uint16_t)0x0FFF) /* Data offset for injected channel 2 */
  1397. /****************** Bit definition for ADC_IOFR3 register *******************/
  1398. #define ADC_JOFFSET3 ((uint16_t)0x0FFF) /* Data offset for injected channel 3 */
  1399. /****************** Bit definition for ADC_IOFR4 register *******************/
  1400. #define ADC_JOFFSET4 ((uint16_t)0x0FFF) /* Data offset for injected channel 4 */
  1401. /******************* Bit definition for ADC_WDHTR register ********************/
  1402. #define ADC_HT ((uint16_t)0x0FFF) /* Analog watchdog high threshold */
  1403. /******************* Bit definition for ADC_WDLTR register ********************/
  1404. #define ADC_LT ((uint16_t)0x0FFF) /* Analog watchdog low threshold */
  1405. /******************* Bit definition for ADC_RSQR1 register *******************/
  1406. #define ADC_SQ13 ((uint32_t)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */
  1407. #define ADC_SQ13_0 ((uint32_t)0x00000001) /* Bit 0 */
  1408. #define ADC_SQ13_1 ((uint32_t)0x00000002) /* Bit 1 */
  1409. #define ADC_SQ13_2 ((uint32_t)0x00000004) /* Bit 2 */
  1410. #define ADC_SQ13_3 ((uint32_t)0x00000008) /* Bit 3 */
  1411. #define ADC_SQ13_4 ((uint32_t)0x00000010) /* Bit 4 */
  1412. #define ADC_SQ14 ((uint32_t)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */
  1413. #define ADC_SQ14_0 ((uint32_t)0x00000020) /* Bit 0 */
  1414. #define ADC_SQ14_1 ((uint32_t)0x00000040) /* Bit 1 */
  1415. #define ADC_SQ14_2 ((uint32_t)0x00000080) /* Bit 2 */
  1416. #define ADC_SQ14_3 ((uint32_t)0x00000100) /* Bit 3 */
  1417. #define ADC_SQ14_4 ((uint32_t)0x00000200) /* Bit 4 */
  1418. #define ADC_SQ15 ((uint32_t)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */
  1419. #define ADC_SQ15_0 ((uint32_t)0x00000400) /* Bit 0 */
  1420. #define ADC_SQ15_1 ((uint32_t)0x00000800) /* Bit 1 */
  1421. #define ADC_SQ15_2 ((uint32_t)0x00001000) /* Bit 2 */
  1422. #define ADC_SQ15_3 ((uint32_t)0x00002000) /* Bit 3 */
  1423. #define ADC_SQ15_4 ((uint32_t)0x00004000) /* Bit 4 */
  1424. #define ADC_SQ16 ((uint32_t)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */
  1425. #define ADC_SQ16_0 ((uint32_t)0x00008000) /* Bit 0 */
  1426. #define ADC_SQ16_1 ((uint32_t)0x00010000) /* Bit 1 */
  1427. #define ADC_SQ16_2 ((uint32_t)0x00020000) /* Bit 2 */
  1428. #define ADC_SQ16_3 ((uint32_t)0x00040000) /* Bit 3 */
  1429. #define ADC_SQ16_4 ((uint32_t)0x00080000) /* Bit 4 */
  1430. #define ADC_L ((uint32_t)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */
  1431. #define ADC_L_0 ((uint32_t)0x00100000) /* Bit 0 */
  1432. #define ADC_L_1 ((uint32_t)0x00200000) /* Bit 1 */
  1433. #define ADC_L_2 ((uint32_t)0x00400000) /* Bit 2 */
  1434. #define ADC_L_3 ((uint32_t)0x00800000) /* Bit 3 */
  1435. /******************* Bit definition for ADC_RSQR2 register *******************/
  1436. #define ADC_SQ7 ((uint32_t)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */
  1437. #define ADC_SQ7_0 ((uint32_t)0x00000001) /* Bit 0 */
  1438. #define ADC_SQ7_1 ((uint32_t)0x00000002) /* Bit 1 */
  1439. #define ADC_SQ7_2 ((uint32_t)0x00000004) /* Bit 2 */
  1440. #define ADC_SQ7_3 ((uint32_t)0x00000008) /* Bit 3 */
  1441. #define ADC_SQ7_4 ((uint32_t)0x00000010) /* Bit 4 */
  1442. #define ADC_SQ8 ((uint32_t)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */
  1443. #define ADC_SQ8_0 ((uint32_t)0x00000020) /* Bit 0 */
  1444. #define ADC_SQ8_1 ((uint32_t)0x00000040) /* Bit 1 */
  1445. #define ADC_SQ8_2 ((uint32_t)0x00000080) /* Bit 2 */
  1446. #define ADC_SQ8_3 ((uint32_t)0x00000100) /* Bit 3 */
  1447. #define ADC_SQ8_4 ((uint32_t)0x00000200) /* Bit 4 */
  1448. #define ADC_SQ9 ((uint32_t)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */
  1449. #define ADC_SQ9_0 ((uint32_t)0x00000400) /* Bit 0 */
  1450. #define ADC_SQ9_1 ((uint32_t)0x00000800) /* Bit 1 */
  1451. #define ADC_SQ9_2 ((uint32_t)0x00001000) /* Bit 2 */
  1452. #define ADC_SQ9_3 ((uint32_t)0x00002000) /* Bit 3 */
  1453. #define ADC_SQ9_4 ((uint32_t)0x00004000) /* Bit 4 */
  1454. #define ADC_SQ10 ((uint32_t)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */
  1455. #define ADC_SQ10_0 ((uint32_t)0x00008000) /* Bit 0 */
  1456. #define ADC_SQ10_1 ((uint32_t)0x00010000) /* Bit 1 */
  1457. #define ADC_SQ10_2 ((uint32_t)0x00020000) /* Bit 2 */
  1458. #define ADC_SQ10_3 ((uint32_t)0x00040000) /* Bit 3 */
  1459. #define ADC_SQ10_4 ((uint32_t)0x00080000) /* Bit 4 */
  1460. #define ADC_SQ11 ((uint32_t)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */
  1461. #define ADC_SQ11_0 ((uint32_t)0x00100000) /* Bit 0 */
  1462. #define ADC_SQ11_1 ((uint32_t)0x00200000) /* Bit 1 */
  1463. #define ADC_SQ11_2 ((uint32_t)0x00400000) /* Bit 2 */
  1464. #define ADC_SQ11_3 ((uint32_t)0x00800000) /* Bit 3 */
  1465. #define ADC_SQ11_4 ((uint32_t)0x01000000) /* Bit 4 */
  1466. #define ADC_SQ12 ((uint32_t)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */
  1467. #define ADC_SQ12_0 ((uint32_t)0x02000000) /* Bit 0 */
  1468. #define ADC_SQ12_1 ((uint32_t)0x04000000) /* Bit 1 */
  1469. #define ADC_SQ12_2 ((uint32_t)0x08000000) /* Bit 2 */
  1470. #define ADC_SQ12_3 ((uint32_t)0x10000000) /* Bit 3 */
  1471. #define ADC_SQ12_4 ((uint32_t)0x20000000) /* Bit 4 */
  1472. /******************* Bit definition for ADC_RSQR3 register *******************/
  1473. #define ADC_SQ1 ((uint32_t)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */
  1474. #define ADC_SQ1_0 ((uint32_t)0x00000001) /* Bit 0 */
  1475. #define ADC_SQ1_1 ((uint32_t)0x00000002) /* Bit 1 */
  1476. #define ADC_SQ1_2 ((uint32_t)0x00000004) /* Bit 2 */
  1477. #define ADC_SQ1_3 ((uint32_t)0x00000008) /* Bit 3 */
  1478. #define ADC_SQ1_4 ((uint32_t)0x00000010) /* Bit 4 */
  1479. #define ADC_SQ2 ((uint32_t)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */
  1480. #define ADC_SQ2_0 ((uint32_t)0x00000020) /* Bit 0 */
  1481. #define ADC_SQ2_1 ((uint32_t)0x00000040) /* Bit 1 */
  1482. #define ADC_SQ2_2 ((uint32_t)0x00000080) /* Bit 2 */
  1483. #define ADC_SQ2_3 ((uint32_t)0x00000100) /* Bit 3 */
  1484. #define ADC_SQ2_4 ((uint32_t)0x00000200) /* Bit 4 */
  1485. #define ADC_SQ3 ((uint32_t)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */
  1486. #define ADC_SQ3_0 ((uint32_t)0x00000400) /* Bit 0 */
  1487. #define ADC_SQ3_1 ((uint32_t)0x00000800) /* Bit 1 */
  1488. #define ADC_SQ3_2 ((uint32_t)0x00001000) /* Bit 2 */
  1489. #define ADC_SQ3_3 ((uint32_t)0x00002000) /* Bit 3 */
  1490. #define ADC_SQ3_4 ((uint32_t)0x00004000) /* Bit 4 */
  1491. #define ADC_SQ4 ((uint32_t)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */
  1492. #define ADC_SQ4_0 ((uint32_t)0x00008000) /* Bit 0 */
  1493. #define ADC_SQ4_1 ((uint32_t)0x00010000) /* Bit 1 */
  1494. #define ADC_SQ4_2 ((uint32_t)0x00020000) /* Bit 2 */
  1495. #define ADC_SQ4_3 ((uint32_t)0x00040000) /* Bit 3 */
  1496. #define ADC_SQ4_4 ((uint32_t)0x00080000) /* Bit 4 */
  1497. #define ADC_SQ5 ((uint32_t)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */
  1498. #define ADC_SQ5_0 ((uint32_t)0x00100000) /* Bit 0 */
  1499. #define ADC_SQ5_1 ((uint32_t)0x00200000) /* Bit 1 */
  1500. #define ADC_SQ5_2 ((uint32_t)0x00400000) /* Bit 2 */
  1501. #define ADC_SQ5_3 ((uint32_t)0x00800000) /* Bit 3 */
  1502. #define ADC_SQ5_4 ((uint32_t)0x01000000) /* Bit 4 */
  1503. #define ADC_SQ6 ((uint32_t)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */
  1504. #define ADC_SQ6_0 ((uint32_t)0x02000000) /* Bit 0 */
  1505. #define ADC_SQ6_1 ((uint32_t)0x04000000) /* Bit 1 */
  1506. #define ADC_SQ6_2 ((uint32_t)0x08000000) /* Bit 2 */
  1507. #define ADC_SQ6_3 ((uint32_t)0x10000000) /* Bit 3 */
  1508. #define ADC_SQ6_4 ((uint32_t)0x20000000) /* Bit 4 */
  1509. /******************* Bit definition for ADC_ISQR register *******************/
  1510. #define ADC_JSQ1 ((uint32_t)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */
  1511. #define ADC_JSQ1_0 ((uint32_t)0x00000001) /* Bit 0 */
  1512. #define ADC_JSQ1_1 ((uint32_t)0x00000002) /* Bit 1 */
  1513. #define ADC_JSQ1_2 ((uint32_t)0x00000004) /* Bit 2 */
  1514. #define ADC_JSQ1_3 ((uint32_t)0x00000008) /* Bit 3 */
  1515. #define ADC_JSQ1_4 ((uint32_t)0x00000010) /* Bit 4 */
  1516. #define ADC_JSQ2 ((uint32_t)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */
  1517. #define ADC_JSQ2_0 ((uint32_t)0x00000020) /* Bit 0 */
  1518. #define ADC_JSQ2_1 ((uint32_t)0x00000040) /* Bit 1 */
  1519. #define ADC_JSQ2_2 ((uint32_t)0x00000080) /* Bit 2 */
  1520. #define ADC_JSQ2_3 ((uint32_t)0x00000100) /* Bit 3 */
  1521. #define ADC_JSQ2_4 ((uint32_t)0x00000200) /* Bit 4 */
  1522. #define ADC_JSQ3 ((uint32_t)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */
  1523. #define ADC_JSQ3_0 ((uint32_t)0x00000400) /* Bit 0 */
  1524. #define ADC_JSQ3_1 ((uint32_t)0x00000800) /* Bit 1 */
  1525. #define ADC_JSQ3_2 ((uint32_t)0x00001000) /* Bit 2 */
  1526. #define ADC_JSQ3_3 ((uint32_t)0x00002000) /* Bit 3 */
  1527. #define ADC_JSQ3_4 ((uint32_t)0x00004000) /* Bit 4 */
  1528. #define ADC_JSQ4 ((uint32_t)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */
  1529. #define ADC_JSQ4_0 ((uint32_t)0x00008000) /* Bit 0 */
  1530. #define ADC_JSQ4_1 ((uint32_t)0x00010000) /* Bit 1 */
  1531. #define ADC_JSQ4_2 ((uint32_t)0x00020000) /* Bit 2 */
  1532. #define ADC_JSQ4_3 ((uint32_t)0x00040000) /* Bit 3 */
  1533. #define ADC_JSQ4_4 ((uint32_t)0x00080000) /* Bit 4 */
  1534. #define ADC_JL ((uint32_t)0x00300000) /* JL[1:0] bits (Injected Sequence length) */
  1535. #define ADC_JL_0 ((uint32_t)0x00100000) /* Bit 0 */
  1536. #define ADC_JL_1 ((uint32_t)0x00200000) /* Bit 1 */
  1537. /******************* Bit definition for ADC_IDATAR1 register *******************/
  1538. #define ADC_IDATAR1_JDATA ((uint16_t)0xFFFF) /* Injected data */
  1539. /******************* Bit definition for ADC_IDATAR2 register *******************/
  1540. #define ADC_IDATAR2_JDATA ((uint16_t)0xFFFF) /* Injected data */
  1541. /******************* Bit definition for ADC_IDATAR3 register *******************/
  1542. #define ADC_IDATAR3_JDATA ((uint16_t)0xFFFF) /* Injected data */
  1543. /******************* Bit definition for ADC_IDATAR4 register *******************/
  1544. #define ADC_IDATAR4_JDATA ((uint16_t)0xFFFF) /* Injected data */
  1545. /******************** Bit definition for ADC_RDATAR register ********************/
  1546. #define ADC_RDATAR_DATA ((uint32_t)0x0000FFFF) /* Regular data */
  1547. #define ADC_RDATAR_ADC2DATA ((uint32_t)0xFFFF0000) /* ADC2 data */
  1548. /******************** Bit definition for ADC_AUX register ********************/
  1549. #define ADC_SMP_SEL_0 ((uint32_t)0x00000001) /* channel_0 */
  1550. #define ADC_SMP_SEL_1 ((uint32_t)0x00000002) /* channel_1 */
  1551. #define ADC_SMP_SEL_2 ((uint32_t)0x00000004) /* channel_2 */
  1552. #define ADC_SMP_SEL_3 ((uint32_t)0x00000008) /* channel_3 */
  1553. #define ADC_SMP_SEL_4 ((uint32_t)0x00000010) /* channel_4 */
  1554. #define ADC_SMP_SEL_5 ((uint32_t)0x00000020) /* channel_5 */
  1555. #define ADC_SMP_SEL_6 ((uint32_t)0x00000040) /* channel_6 */
  1556. #define ADC_SMP_SEL_7 ((uint32_t)0x00000080) /* channel_7 */
  1557. #define ADC_SMP_SEL_8 ((uint32_t)0x00000100) /* channel_8 */
  1558. #define ADC_SMP_SEL_9 ((uint32_t)0x00000200) /* channel_9 */
  1559. #define ADC_SMP_SEL_10 ((uint32_t)0x00000400) /* channel_10 */
  1560. #define ADC_SMP_SEL_11 ((uint32_t)0x00000800) /* channel_11 */
  1561. #define ADC_SMP_SEL_12 ((uint32_t)0x00001000) /* channel_12 */
  1562. #define ADC_SMP_SEL_13 ((uint32_t)0x00002000) /* channel_13 */
  1563. #define ADC_SMP_SEL_14 ((uint32_t)0x00004000) /* channel_14 */
  1564. #define ADC_SMP_SEL_15 ((uint32_t)0x00008000) /* channel_15 */
  1565. #define ADC_SMP_SEL_16 ((uint32_t)0x00010000) /* channel_16 */
  1566. #define ADC_SMP_SEL_17 ((uint32_t)0x00020000) /* channel_17 */
  1567. /******************************************************************************/
  1568. /* Backup registers */
  1569. /******************************************************************************/
  1570. /******************* Bit definition for BKP_DATAR1 register ********************/
  1571. #define BKP_DATAR1_D ((uint16_t)0xFFFF) /* Backup data */
  1572. /******************* Bit definition for BKP_DATAR2 register ********************/
  1573. #define BKP_DATAR2_D ((uint16_t)0xFFFF) /* Backup data */
  1574. /******************* Bit definition for BKP_DATAR3 register ********************/
  1575. #define BKP_DATAR3_D ((uint16_t)0xFFFF) /* Backup data */
  1576. /******************* Bit definition for BKP_DATAR4 register ********************/
  1577. #define BKP_DATAR4_D ((uint16_t)0xFFFF) /* Backup data */
  1578. /******************* Bit definition for BKP_DATAR5 register ********************/
  1579. #define BKP_DATAR5_D ((uint16_t)0xFFFF) /* Backup data */
  1580. /******************* Bit definition for BKP_DATAR6 register ********************/
  1581. #define BKP_DATAR6_D ((uint16_t)0xFFFF) /* Backup data */
  1582. /******************* Bit definition for BKP_DATAR7 register ********************/
  1583. #define BKP_DATAR7_D ((uint16_t)0xFFFF) /* Backup data */
  1584. /******************* Bit definition for BKP_DATAR8 register ********************/
  1585. #define BKP_DATAR8_D ((uint16_t)0xFFFF) /* Backup data */
  1586. /******************* Bit definition for BKP_DATAR9 register ********************/
  1587. #define BKP_DATAR9_D ((uint16_t)0xFFFF) /* Backup data */
  1588. /******************* Bit definition for BKP_DATAR10 register *******************/
  1589. #define BKP_DATAR10_D ((uint16_t)0xFFFF) /* Backup data */
  1590. /******************* Bit definition for BKP_DATAR11 register *******************/
  1591. #define BKP_DATAR11_D ((uint16_t)0xFFFF) /* Backup data */
  1592. /******************* Bit definition for BKP_DATAR12 register *******************/
  1593. #define BKP_DATAR12_D ((uint16_t)0xFFFF) /* Backup data */
  1594. /******************* Bit definition for BKP_DATAR13 register *******************/
  1595. #define BKP_DATAR13_D ((uint16_t)0xFFFF) /* Backup data */
  1596. /******************* Bit definition for BKP_DATAR14 register *******************/
  1597. #define BKP_DATAR14_D ((uint16_t)0xFFFF) /* Backup data */
  1598. /******************* Bit definition for BKP_DATAR15 register *******************/
  1599. #define BKP_DATAR15_D ((uint16_t)0xFFFF) /* Backup data */
  1600. /******************* Bit definition for BKP_DATAR16 register *******************/
  1601. #define BKP_DATAR16_D ((uint16_t)0xFFFF) /* Backup data */
  1602. /******************* Bit definition for BKP_DATAR17 register *******************/
  1603. #define BKP_DATAR17_D ((uint16_t)0xFFFF) /* Backup data */
  1604. /****************** Bit definition for BKP_DATAR18 register ********************/
  1605. #define BKP_DATAR18_D ((uint16_t)0xFFFF) /* Backup data */
  1606. /******************* Bit definition for BKP_DATAR19 register *******************/
  1607. #define BKP_DATAR19_D ((uint16_t)0xFFFF) /* Backup data */
  1608. /******************* Bit definition for BKP_DATAR20 register *******************/
  1609. #define BKP_DATAR20_D ((uint16_t)0xFFFF) /* Backup data */
  1610. /******************* Bit definition for BKP_DATAR21 register *******************/
  1611. #define BKP_DATAR21_D ((uint16_t)0xFFFF) /* Backup data */
  1612. /******************* Bit definition for BKP_DATAR22 register *******************/
  1613. #define BKP_DATAR22_D ((uint16_t)0xFFFF) /* Backup data */
  1614. /******************* Bit definition for BKP_DATAR23 register *******************/
  1615. #define BKP_DATAR23_D ((uint16_t)0xFFFF) /* Backup data */
  1616. /******************* Bit definition for BKP_DATAR24 register *******************/
  1617. #define BKP_DATAR24_D ((uint16_t)0xFFFF) /* Backup data */
  1618. /******************* Bit definition for BKP_DATAR25 register *******************/
  1619. #define BKP_DATAR25_D ((uint16_t)0xFFFF) /* Backup data */
  1620. /******************* Bit definition for BKP_DATAR26 register *******************/
  1621. #define BKP_DATAR26_D ((uint16_t)0xFFFF) /* Backup data */
  1622. /******************* Bit definition for BKP_DATAR27 register *******************/
  1623. #define BKP_DATAR27_D ((uint16_t)0xFFFF) /* Backup data */
  1624. /******************* Bit definition for BKP_DATAR28 register *******************/
  1625. #define BKP_DATAR28_D ((uint16_t)0xFFFF) /* Backup data */
  1626. /******************* Bit definition for BKP_DATAR29 register *******************/
  1627. #define BKP_DATAR29_D ((uint16_t)0xFFFF) /* Backup data */
  1628. /******************* Bit definition for BKP_DATAR30 register *******************/
  1629. #define BKP_DATAR30_D ((uint16_t)0xFFFF) /* Backup data */
  1630. /******************* Bit definition for BKP_DATAR31 register *******************/
  1631. #define BKP_DATAR31_D ((uint16_t)0xFFFF) /* Backup data */
  1632. /******************* Bit definition for BKP_DATAR32 register *******************/
  1633. #define BKP_DATAR32_D ((uint16_t)0xFFFF) /* Backup data */
  1634. /******************* Bit definition for BKP_DATAR33 register *******************/
  1635. #define BKP_DATAR33_D ((uint16_t)0xFFFF) /* Backup data */
  1636. /******************* Bit definition for BKP_DATAR34 register *******************/
  1637. #define BKP_DATAR34_D ((uint16_t)0xFFFF) /* Backup data */
  1638. /******************* Bit definition for BKP_DATAR35 register *******************/
  1639. #define BKP_DATAR35_D ((uint16_t)0xFFFF) /* Backup data */
  1640. /******************* Bit definition for BKP_DATAR36 register *******************/
  1641. #define BKP_DATAR36_D ((uint16_t)0xFFFF) /* Backup data */
  1642. /******************* Bit definition for BKP_DATAR37 register *******************/
  1643. #define BKP_DATAR37_D ((uint16_t)0xFFFF) /* Backup data */
  1644. /******************* Bit definition for BKP_DATAR38 register *******************/
  1645. #define BKP_DATAR38_D ((uint16_t)0xFFFF) /* Backup data */
  1646. /******************* Bit definition for BKP_DATAR39 register *******************/
  1647. #define BKP_DATAR39_D ((uint16_t)0xFFFF) /* Backup data */
  1648. /******************* Bit definition for BKP_DATAR40 register *******************/
  1649. #define BKP_DATAR40_D ((uint16_t)0xFFFF) /* Backup data */
  1650. /******************* Bit definition for BKP_DATAR41 register *******************/
  1651. #define BKP_DATAR41_D ((uint16_t)0xFFFF) /* Backup data */
  1652. /******************* Bit definition for BKP_DATAR42 register *******************/
  1653. #define BKP_DATAR42_D ((uint16_t)0xFFFF) /* Backup data */
  1654. /****************** Bit definition for BKP_OCTLR register *******************/
  1655. #define BKP_CAL ((uint16_t)0x007F) /* Calibration value */
  1656. #define BKP_CCO ((uint16_t)0x0080) /* Calibration Clock Output */
  1657. #define BKP_ASOE ((uint16_t)0x0100) /* Alarm or Second Output Enable */
  1658. #define BKP_ASOS ((uint16_t)0x0200) /* Alarm or Second Output Selection */
  1659. /******************** Bit definition for BKP_TPCTLR register ********************/
  1660. #define BKP_TPE ((uint8_t)0x01) /* TAMPER pin enable */
  1661. #define BKP_TPAL ((uint8_t)0x02) /* TAMPER pin active level */
  1662. /******************* Bit definition for BKP_TPCSR register ********************/
  1663. #define BKP_CTE ((uint16_t)0x0001) /* Clear Tamper event */
  1664. #define BKP_CTI ((uint16_t)0x0002) /* Clear Tamper Interrupt */
  1665. #define BKP_TPIE ((uint16_t)0x0004) /* TAMPER Pin interrupt enable */
  1666. #define BKP_TEF ((uint16_t)0x0100) /* Tamper Event Flag */
  1667. #define BKP_TIF ((uint16_t)0x0200) /* Tamper Interrupt Flag */
  1668. /******************************************************************************/
  1669. /* Controller Area Network */
  1670. /******************************************************************************/
  1671. /******************* Bit definition for CAN_CTLR register ********************/
  1672. #define CAN_CTLR_INRQ ((uint16_t)0x0001) /* Initialization Request */
  1673. #define CAN_CTLR_SLEEP ((uint16_t)0x0002) /* Sleep Mode Request */
  1674. #define CAN_CTLR_TXFP ((uint16_t)0x0004) /* Transmit FIFO Priority */
  1675. #define CAN_CTLR_RFLM ((uint16_t)0x0008) /* Receive FIFO Locked Mode */
  1676. #define CAN_CTLR_NART ((uint16_t)0x0010) /* No Automatic Retransmission */
  1677. #define CAN_CTLR_AWUM ((uint16_t)0x0020) /* Automatic Wakeup Mode */
  1678. #define CAN_CTLR_ABOM ((uint16_t)0x0040) /* Automatic Bus-Off Management */
  1679. #define CAN_CTLR_TTCM ((uint16_t)0x0080) /* Time Triggered Communication Mode */
  1680. #define CAN_CTLR_RESET ((uint16_t)0x8000) /* CAN software master reset */
  1681. #define CAN_CTLR_DBF ((uint32_t)0x10000)
  1682. /******************* Bit definition for CAN_STATR register ********************/
  1683. #define CAN_STATR_INAK ((uint16_t)0x0001) /* Initialization Acknowledge */
  1684. #define CAN_STATR_SLAK ((uint16_t)0x0002) /* Sleep Acknowledge */
  1685. #define CAN_STATR_ERRI ((uint16_t)0x0004) /* Error Interrupt */
  1686. #define CAN_STATR_WKUI ((uint16_t)0x0008) /* Wakeup Interrupt */
  1687. #define CAN_STATR_SLAKI ((uint16_t)0x0010) /* Sleep Acknowledge Interrupt */
  1688. #define CAN_STATR_TXM ((uint16_t)0x0100) /* Transmit Mode */
  1689. #define CAN_STATR_RXM ((uint16_t)0x0200) /* Receive Mode */
  1690. #define CAN_STATR_SAMP ((uint16_t)0x0400) /* Last Sample Point */
  1691. #define CAN_STATR_RX ((uint16_t)0x0800) /* CAN Rx Signal */
  1692. /******************* Bit definition for CAN_TSTATR register ********************/
  1693. #define CAN_TSTATR_RQCP0 ((uint32_t)0x00000001) /* Request Completed Mailbox0 */
  1694. #define CAN_TSTATR_TXOK0 ((uint32_t)0x00000002) /* Transmission OK of Mailbox0 */
  1695. #define CAN_TSTATR_ALST0 ((uint32_t)0x00000004) /* Arbitration Lost for Mailbox0 */
  1696. #define CAN_TSTATR_TERR0 ((uint32_t)0x00000008) /* Transmission Error of Mailbox0 */
  1697. #define CAN_TSTATR_ABRQ0 ((uint32_t)0x00000080) /* Abort Request for Mailbox0 */
  1698. #define CAN_TSTATR_RQCP1 ((uint32_t)0x00000100) /* Request Completed Mailbox1 */
  1699. #define CAN_TSTATR_TXOK1 ((uint32_t)0x00000200) /* Transmission OK of Mailbox1 */
  1700. #define CAN_TSTATR_ALST1 ((uint32_t)0x00000400) /* Arbitration Lost for Mailbox1 */
  1701. #define CAN_TSTATR_TERR1 ((uint32_t)0x00000800) /* Transmission Error of Mailbox1 */
  1702. #define CAN_TSTATR_ABRQ1 ((uint32_t)0x00008000) /* Abort Request for Mailbox 1 */
  1703. #define CAN_TSTATR_RQCP2 ((uint32_t)0x00010000) /* Request Completed Mailbox2 */
  1704. #define CAN_TSTATR_TXOK2 ((uint32_t)0x00020000) /* Transmission OK of Mailbox 2 */
  1705. #define CAN_TSTATR_ALST2 ((uint32_t)0x00040000) /* Arbitration Lost for mailbox 2 */
  1706. #define CAN_TSTATR_TERR2 ((uint32_t)0x00080000) /* Transmission Error of Mailbox 2 */
  1707. #define CAN_TSTATR_ABRQ2 ((uint32_t)0x00800000) /* Abort Request for Mailbox 2 */
  1708. #define CAN_TSTATR_CODE ((uint32_t)0x03000000) /* Mailbox Code */
  1709. #define CAN_TSTATR_TME ((uint32_t)0x1C000000) /* TME[2:0] bits */
  1710. #define CAN_TSTATR_TME0 ((uint32_t)0x04000000) /* Transmit Mailbox 0 Empty */
  1711. #define CAN_TSTATR_TME1 ((uint32_t)0x08000000) /* Transmit Mailbox 1 Empty */
  1712. #define CAN_TSTATR_TME2 ((uint32_t)0x10000000) /* Transmit Mailbox 2 Empty */
  1713. #define CAN_TSTATR_LOW ((uint32_t)0xE0000000) /* LOW[2:0] bits */
  1714. #define CAN_TSTATR_LOW0 ((uint32_t)0x20000000) /* Lowest Priority Flag for Mailbox 0 */
  1715. #define CAN_TSTATR_LOW1 ((uint32_t)0x40000000) /* Lowest Priority Flag for Mailbox 1 */
  1716. #define CAN_TSTATR_LOW2 ((uint32_t)0x80000000) /* Lowest Priority Flag for Mailbox 2 */
  1717. /******************* Bit definition for CAN_RFIFO0 register *******************/
  1718. #define CAN_RFIFO0_FMP0 ((uint8_t)0x03) /* FIFO 0 Message Pending */
  1719. #define CAN_RFIFO0_FULL0 ((uint8_t)0x08) /* FIFO 0 Full */
  1720. #define CAN_RFIFO0_FOVR0 ((uint8_t)0x10) /* FIFO 0 Overrun */
  1721. #define CAN_RFIFO0_RFOM0 ((uint8_t)0x20) /* Release FIFO 0 Output Mailbox */
  1722. /******************* Bit definition for CAN_RFIFO1 register *******************/
  1723. #define CAN_RFIFO1_FMP1 ((uint8_t)0x03) /* FIFO 1 Message Pending */
  1724. #define CAN_RFIFO1_FULL1 ((uint8_t)0x08) /* FIFO 1 Full */
  1725. #define CAN_RFIFO1_FOVR1 ((uint8_t)0x10) /* FIFO 1 Overrun */
  1726. #define CAN_RFIFO1_RFOM1 ((uint8_t)0x20) /* Release FIFO 1 Output Mailbox */
  1727. /******************** Bit definition for CAN_INTENR register *******************/
  1728. #define CAN_INTENR_TMEIE ((uint32_t)0x00000001) /* Transmit Mailbox Empty Interrupt Enable */
  1729. #define CAN_INTENR_FMPIE0 ((uint32_t)0x00000002) /* FIFO Message Pending Interrupt Enable */
  1730. #define CAN_INTENR_FFIE0 ((uint32_t)0x00000004) /* FIFO Full Interrupt Enable */
  1731. #define CAN_INTENR_FOVIE0 ((uint32_t)0x00000008) /* FIFO Overrun Interrupt Enable */
  1732. #define CAN_INTENR_FMPIE1 ((uint32_t)0x00000010) /* FIFO Message Pending Interrupt Enable */
  1733. #define CAN_INTENR_FFIE1 ((uint32_t)0x00000020) /* FIFO Full Interrupt Enable */
  1734. #define CAN_INTENR_FOVIE1 ((uint32_t)0x00000040) /* FIFO Overrun Interrupt Enable */
  1735. #define CAN_INTENR_EWGIE ((uint32_t)0x00000100) /* Error Warning Interrupt Enable */
  1736. #define CAN_INTENR_EPVIE ((uint32_t)0x00000200) /* Error Passive Interrupt Enable */
  1737. #define CAN_INTENR_BOFIE ((uint32_t)0x00000400) /* Bus-Off Interrupt Enable */
  1738. #define CAN_INTENR_LECIE ((uint32_t)0x00000800) /* Last Error Code Interrupt Enable */
  1739. #define CAN_INTENR_ERRIE ((uint32_t)0x00008000) /* Error Interrupt Enable */
  1740. #define CAN_INTENR_WKUIE ((uint32_t)0x00010000) /* Wakeup Interrupt Enable */
  1741. #define CAN_INTENR_SLKIE ((uint32_t)0x00020000) /* Sleep Interrupt Enable */
  1742. /******************** Bit definition for CAN_ERRSR register *******************/
  1743. #define CAN_ERRSR_EWGF ((uint32_t)0x00000001) /* Error Warning Flag */
  1744. #define CAN_ERRSR_EPVF ((uint32_t)0x00000002) /* Error Passive Flag */
  1745. #define CAN_ERRSR_BOFF ((uint32_t)0x00000004) /* Bus-Off Flag */
  1746. #define CAN_ERRSR_LEC ((uint32_t)0x00000070) /* LEC[2:0] bits (Last Error Code) */
  1747. #define CAN_ERRSR_LEC_0 ((uint32_t)0x00000010) /* Bit 0 */
  1748. #define CAN_ERRSR_LEC_1 ((uint32_t)0x00000020) /* Bit 1 */
  1749. #define CAN_ERRSR_LEC_2 ((uint32_t)0x00000040) /* Bit 2 */
  1750. #define CAN_ERRSR_TEC ((uint32_t)0x00FF0000) /* Least significant byte of the 9-bit Transmit Error Counter */
  1751. #define CAN_ERRSR_REC ((uint32_t)0xFF000000) /* Receive Error Counter */
  1752. /******************* Bit definition for CAN_TTCTLR register ********************/
  1753. #define CAN_TTCTLR_TIMCMV ((uint32_t)0x0000FFFF)
  1754. #define CAN_TTCTLR_TIMRST ((uint32_t)0x00010000)
  1755. #define CAN_TTCTLR_MODE ((uint32_t)0x00020000)
  1756. /******************* Bit definition for CAN_TTCNT register ********************/
  1757. #define CAN_TTCNT_TIMCNT ((uint32_t)0x0000FFFF)
  1758. /****************** Bit definition for CAN_TXMI0R register ********************/
  1759. #define CAN_TXMI0R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */
  1760. #define CAN_TXMI0R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */
  1761. #define CAN_TXMI0R_IDE ((uint32_t)0x00000004) /* Identifier Extension */
  1762. #define CAN_TXMI0R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */
  1763. #define CAN_TXMI0R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */
  1764. /****************** Bit definition for CAN_TXMDT0R register *******************/
  1765. #define CAN_TXMDT0R_DLC ((uint32_t)0x0000000F) /* Data Length Code */
  1766. #define CAN_TXMDT0R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */
  1767. #define CAN_TXMDT0R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */
  1768. /****************** Bit definition for CAN_TXMDL0R register *******************/
  1769. #define CAN_TXMDL0R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */
  1770. #define CAN_TXMDL0R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */
  1771. #define CAN_TXMDL0R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */
  1772. #define CAN_TXMDL0R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */
  1773. /****************** Bit definition for CAN_TXMDH0R register *******************/
  1774. #define CAN_TXMDH0R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */
  1775. #define CAN_TXMDH0R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */
  1776. #define CAN_TXMDH0R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */
  1777. #define CAN_TXMDH0R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */
  1778. /******************* Bit definition for CAN_TXMI1R register *******************/
  1779. #define CAN_TXMI1R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */
  1780. #define CAN_TXMI1R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */
  1781. #define CAN_TXMI1R_IDE ((uint32_t)0x00000004) /* Identifier Extension */
  1782. #define CAN_TXMI1R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */
  1783. #define CAN_TXMI1R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */
  1784. /******************* Bit definition for CAN_TXMDT1R register ******************/
  1785. #define CAN_TXMDT1R_DLC ((uint32_t)0x0000000F) /* Data Length Code */
  1786. #define CAN_TXMDT1R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */
  1787. #define CAN_TXMDT1R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */
  1788. /******************* Bit definition for CAN_TXMDL1R register ******************/
  1789. #define CAN_TXMDL1R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */
  1790. #define CAN_TXMDL1R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */
  1791. #define CAN_TXMDL1R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */
  1792. #define CAN_TXMDL1R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */
  1793. /******************* Bit definition for CAN_TXMDH1R register ******************/
  1794. #define CAN_TXMDH1R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */
  1795. #define CAN_TXMDH1R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */
  1796. #define CAN_TXMDH1R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */
  1797. #define CAN_TXMDH1R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */
  1798. /******************* Bit definition for CAN_TXMI2R register *******************/
  1799. #define CAN_TXMI2R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */
  1800. #define CAN_TXMI2R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */
  1801. #define CAN_TXMI2R_IDE ((uint32_t)0x00000004) /* Identifier Extension */
  1802. #define CAN_TXMI2R_EXID ((uint32_t)0x001FFFF8) /* Extended identifier */
  1803. #define CAN_TXMI2R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */
  1804. /******************* Bit definition for CAN_TXMDT2R register ******************/
  1805. #define CAN_TXMDT2R_DLC ((uint32_t)0x0000000F) /* Data Length Code */
  1806. #define CAN_TXMDT2R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */
  1807. #define CAN_TXMDT2R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */
  1808. /******************* Bit definition for CAN_TXMDL2R register ******************/
  1809. #define CAN_TXMDL2R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */
  1810. #define CAN_TXMDL2R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */
  1811. #define CAN_TXMDL2R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */
  1812. #define CAN_TXMDL2R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */
  1813. /******************* Bit definition for CAN_TXMDH2R register ******************/
  1814. #define CAN_TXMDH2R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */
  1815. #define CAN_TXMDH2R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */
  1816. #define CAN_TXMDH2R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */
  1817. #define CAN_TXMDH2R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */
  1818. /******************* Bit definition for CAN_RXMI0R register *******************/
  1819. #define CAN_RXMI0R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */
  1820. #define CAN_RXMI0R_IDE ((uint32_t)0x00000004) /* Identifier Extension */
  1821. #define CAN_RXMI0R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */
  1822. #define CAN_RXMI0R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */
  1823. /******************* Bit definition for CAN_RXMDT0R register ******************/
  1824. #define CAN_RXMDT0R_DLC ((uint32_t)0x0000000F) /* Data Length Code */
  1825. #define CAN_RXMDT0R_FMI ((uint32_t)0x0000FF00) /* Filter Match Index */
  1826. #define CAN_RXMDT0R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */
  1827. /******************* Bit definition for CAN_RXMDL0R register ******************/
  1828. #define CAN_RXMDL0R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */
  1829. #define CAN_RXMDL0R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */
  1830. #define CAN_RXMDL0R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */
  1831. #define CAN_RXMDL0R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */
  1832. /******************* Bit definition for CAN_RXMDH0R register ******************/
  1833. #define CAN_RXMDH0R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */
  1834. #define CAN_RXMDH0R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */
  1835. #define CAN_RXMDH0R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */
  1836. #define CAN_RXMDH0R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */
  1837. /******************* Bit definition for CAN_RXMI1R register *******************/
  1838. #define CAN_RXMI1R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */
  1839. #define CAN_RXMI1R_IDE ((uint32_t)0x00000004) /* Identifier Extension */
  1840. #define CAN_RXMI1R_EXID ((uint32_t)0x001FFFF8) /* Extended identifier */
  1841. #define CAN_RXMI1R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */
  1842. /******************* Bit definition for CAN_RXMDT1R register ******************/
  1843. #define CAN_RXMDT1R_DLC ((uint32_t)0x0000000F) /* Data Length Code */
  1844. #define CAN_RXMDT1R_FMI ((uint32_t)0x0000FF00) /* Filter Match Index */
  1845. #define CAN_RXMDT1R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */
  1846. /******************* Bit definition for CAN_RXMDL1R register ******************/
  1847. #define CAN_RXMDL1R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */
  1848. #define CAN_RXMDL1R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */
  1849. #define CAN_RXMDL1R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */
  1850. #define CAN_RXMDL1R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */
  1851. /******************* Bit definition for CAN_RXMDH1R register ******************/
  1852. #define CAN_RXMDH1R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */
  1853. #define CAN_RXMDH1R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */
  1854. #define CAN_RXMDH1R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */
  1855. #define CAN_RXMDH1R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */
  1856. /******************* Bit definition for CAN_FCTLR register ********************/
  1857. #define CAN_FCTLR_FINIT ((uint8_t)0x01) /* Filter Init Mode */
  1858. #define CAN_FCTLR_CAN2SB ((uint16_t)0x3F00)
  1859. /******************* Bit definition for CAN_FMCFGR register *******************/
  1860. #define CAN_FMCFGR_FBM ((uint16_t)0x3FFF) /* Filter Mode */
  1861. #define CAN_FMCFGR_FBM0 ((uint16_t)0x0001) /* Filter Init Mode bit 0 */
  1862. #define CAN_FMCFGR_FBM1 ((uint16_t)0x0002) /* Filter Init Mode bit 1 */
  1863. #define CAN_FMCFGR_FBM2 ((uint16_t)0x0004) /* Filter Init Mode bit 2 */
  1864. #define CAN_FMCFGR_FBM3 ((uint16_t)0x0008) /* Filter Init Mode bit 3 */
  1865. #define CAN_FMCFGR_FBM4 ((uint16_t)0x0010) /* Filter Init Mode bit 4 */
  1866. #define CAN_FMCFGR_FBM5 ((uint16_t)0x0020) /* Filter Init Mode bit 5 */
  1867. #define CAN_FMCFGR_FBM6 ((uint16_t)0x0040) /* Filter Init Mode bit 6 */
  1868. #define CAN_FMCFGR_FBM7 ((uint16_t)0x0080) /* Filter Init Mode bit 7 */
  1869. #define CAN_FMCFGR_FBM8 ((uint16_t)0x0100) /* Filter Init Mode bit 8 */
  1870. #define CAN_FMCFGR_FBM9 ((uint16_t)0x0200) /* Filter Init Mode bit 9 */
  1871. #define CAN_FMCFGR_FBM10 ((uint16_t)0x0400) /* Filter Init Mode bit 10 */
  1872. #define CAN_FMCFGR_FBM11 ((uint16_t)0x0800) /* Filter Init Mode bit 11 */
  1873. #define CAN_FMCFGR_FBM12 ((uint16_t)0x1000) /* Filter Init Mode bit 12 */
  1874. #define CAN_FMCFGR_FBM13 ((uint16_t)0x2000) /* Filter Init Mode bit 13 */
  1875. #define CAN_FMCFGR_FBM14 ((uint16_t)0x4000) /* Filter Init Mode bit 14 */
  1876. #define CAN_FMCFGR_FBM15 ((uint16_t)0x8000) /* Filter Init Mode bit 15 */
  1877. #define CAN_FMCFGR_FBM16 ((uint32_t)0x10000) /* Filter Init Mode bit 16 */
  1878. #define CAN_FMCFGR_FBM17 ((uint32_t)0x20000) /* Filter Init Mode bit 17 */
  1879. #define CAN_FMCFGR_FBM18 ((uint32_t)0x40000) /* Filter Init Mode bit 18 */
  1880. #define CAN_FMCFGR_FBM19 ((uint32_t)0x80000) /* Filter Init Mode bit 19 */
  1881. #define CAN_FMCFGR_FBM20 ((uint32_t)0x100000) /* Filter Init Mode bit 20 */
  1882. #define CAN_FMCFGR_FBM21 ((uint32_t)0x200000) /* Filter Init Mode bit 21 */
  1883. #define CAN_FMCFGR_FBM22 ((uint32_t)0x400000) /* Filter Init Mode bit 22 */
  1884. #define CAN_FMCFGR_FBM23 ((uint32_t)0x800000) /* Filter Init Mode bit 23 */
  1885. #define CAN_FMCFGR_FBM24 ((uint32_t)0x1000000) /* Filter Init Mode bit 24 */
  1886. #define CAN_FMCFGR_FBM25 ((uint32_t)0x2000000) /* Filter Init Mode bit 25 */
  1887. #define CAN_FMCFGR_FBM26 ((uint32_t)0x4000000) /* Filter Init Mode bit 26 */
  1888. #define CAN_FMCFGR_FBM27 ((uint32_t)0x8000000) /* Filter Init Mode bit 27 */
  1889. /******************* Bit definition for CAN_FSCFGR register *******************/
  1890. #define CAN_FSCFGR_FSC ((uint16_t)0x3FFF) /* Filter Scale Configuration */
  1891. #define CAN_FSCFGR_FSC0 ((uint16_t)0x0001) /* Filter Scale Configuration bit 0 */
  1892. #define CAN_FSCFGR_FSC1 ((uint16_t)0x0002) /* Filter Scale Configuration bit 1 */
  1893. #define CAN_FSCFGR_FSC2 ((uint16_t)0x0004) /* Filter Scale Configuration bit 2 */
  1894. #define CAN_FSCFGR_FSC3 ((uint16_t)0x0008) /* Filter Scale Configuration bit 3 */
  1895. #define CAN_FSCFGR_FSC4 ((uint16_t)0x0010) /* Filter Scale Configuration bit 4 */
  1896. #define CAN_FSCFGR_FSC5 ((uint16_t)0x0020) /* Filter Scale Configuration bit 5 */
  1897. #define CAN_FSCFGR_FSC6 ((uint16_t)0x0040) /* Filter Scale Configuration bit 6 */
  1898. #define CAN_FSCFGR_FSC7 ((uint16_t)0x0080) /* Filter Scale Configuration bit 7 */
  1899. #define CAN_FSCFGR_FSC8 ((uint16_t)0x0100) /* Filter Scale Configuration bit 8 */
  1900. #define CAN_FSCFGR_FSC9 ((uint16_t)0x0200) /* Filter Scale Configuration bit 9 */
  1901. #define CAN_FSCFGR_FSC10 ((uint16_t)0x0400) /* Filter Scale Configuration bit 10 */
  1902. #define CAN_FSCFGR_FSC11 ((uint16_t)0x0800) /* Filter Scale Configuration bit 11 */
  1903. #define CAN_FSCFGR_FSC12 ((uint16_t)0x1000) /* Filter Scale Configuration bit 12 */
  1904. #define CAN_FSCFGR_FSC13 ((uint16_t)0x2000) /* Filter Scale Configuration bit 13 */
  1905. #define CAN_FSCFGR_FSC14 ((uint16_t)0x4000) /* Filter Scale Configuration bit 14 */
  1906. #define CAN_FSCFGR_FSC15 ((uint16_t)0x8000) /* Filter Scale Configuration bit 15 */
  1907. #define CAN_FSCFGR_FSC16 ((uint32_t)0x10000) /* Filter Scale Configuration bit 16 */
  1908. #define CAN_FSCFGR_FSC17 ((uint32_t)0x20000) /* Filter Scale Configuration bit 17 */
  1909. #define CAN_FSCFGR_FSC18 ((uint32_t)0x40000) /* Filter Scale Configuration bit 18 */
  1910. #define CAN_FSCFGR_FSC19 ((uint32_t)0x80000) /* Filter Scale Configuration bit 19 */
  1911. #define CAN_FSCFGR_FSC20 ((uint32_t)0x100000) /* Filter Scale Configuration bit 20 */
  1912. #define CAN_FSCFGR_FSC21 ((uint32_t)0x200000) /* Filter Scale Configuration bit 21 */
  1913. #define CAN_FSCFGR_FSC22 ((uint32_t)0x400000) /* Filter Scale Configuration bit 22 */
  1914. #define CAN_FSCFGR_FSC23 ((uint32_t)0x800000) /* Filter Scale Configuration bit 23 */
  1915. #define CAN_FSCFGR_FSC24 ((uint32_t)0x1000000) /* Filter Scale Configuration bit 24 */
  1916. #define CAN_FSCFGR_FSC25 ((uint32_t)0x2000000) /* Filter Scale Configuration bit 25 */
  1917. #define CAN_FSCFGR_FSC26 ((uint32_t)0x4000000) /* Filter Scale Configuration bit 26 */
  1918. #define CAN_FSCFGR_FSC27 ((uint32_t)0x8000000) /* Filter Scale Configuration bit 27 */
  1919. /****************** Bit definition for CAN_FAFIFOR register *******************/
  1920. #define CAN_FAFIFOR_FFA ((uint16_t)0x3FFF) /* Filter FIFO Assignment */
  1921. #define CAN_FAFIFOR_FFA0 ((uint16_t)0x0001) /* Filter FIFO Assignment for Filter 0 */
  1922. #define CAN_FAFIFOR_FFA1 ((uint16_t)0x0002) /* Filter FIFO Assignment for Filter 1 */
  1923. #define CAN_FAFIFOR_FFA2 ((uint16_t)0x0004) /* Filter FIFO Assignment for Filter 2 */
  1924. #define CAN_FAFIFOR_FFA3 ((uint16_t)0x0008) /* Filter FIFO Assignment for Filter 3 */
  1925. #define CAN_FAFIFOR_FFA4 ((uint16_t)0x0010) /* Filter FIFO Assignment for Filter 4 */
  1926. #define CAN_FAFIFOR_FFA5 ((uint16_t)0x0020) /* Filter FIFO Assignment for Filter 5 */
  1927. #define CAN_FAFIFOR_FFA6 ((uint16_t)0x0040) /* Filter FIFO Assignment for Filter 6 */
  1928. #define CAN_FAFIFOR_FFA7 ((uint16_t)0x0080) /* Filter FIFO Assignment for Filter 7 */
  1929. #define CAN_FAFIFOR_FFA8 ((uint16_t)0x0100) /* Filter FIFO Assignment for Filter 8 */
  1930. #define CAN_FAFIFOR_FFA9 ((uint16_t)0x0200) /* Filter FIFO Assignment for Filter 9 */
  1931. #define CAN_FAFIFOR_FFA10 ((uint16_t)0x0400) /* Filter FIFO Assignment for Filter 10 */
  1932. #define CAN_FAFIFOR_FFA11 ((uint16_t)0x0800) /* Filter FIFO Assignment for Filter 11 */
  1933. #define CAN_FAFIFOR_FFA12 ((uint16_t)0x1000) /* Filter FIFO Assignment for Filter 12 */
  1934. #define CAN_FAFIFOR_FFA13 ((uint16_t)0x2000) /* Filter FIFO Assignment for Filter 13 */
  1935. #define CAN_FAFIFOR_FFA14 ((uint32_t)0x4000) /* Filter FIFO Assignment for Filter 14 */
  1936. #define CAN_FAFIFOR_FFA15 ((uint32_t)0x8000) /* Filter FIFO Assignment for Filter 15 */
  1937. #define CAN_FAFIFOR_FFA16 ((uint32_t)0x10000) /* Filter FIFO Assignment for Filter 16 */
  1938. #define CAN_FAFIFOR_FFA17 ((uint32_t)0x20000) /* Filter FIFO Assignment for Filter 17 */
  1939. #define CAN_FAFIFOR_FFA18 ((uint32_t)0x40000) /* Filter FIFO Assignment for Filter 18 */
  1940. #define CAN_FAFIFOR_FFA19 ((uint32_t)0x80000) /* Filter FIFO Assignment for Filter 19 */
  1941. #define CAN_FAFIFOR_FFA20 ((uint32_t)0x100000) /* Filter FIFO Assignment for Filter 20 */
  1942. #define CAN_FAFIFOR_FFA21 ((uint32_t)0x200000) /* Filter FIFO Assignment for Filter 21 */
  1943. #define CAN_FAFIFOR_FFA22 ((uint32_t)0x400000) /* Filter FIFO Assignment for Filter 22 */
  1944. #define CAN_FAFIFOR_FFA23 ((uint32_t)0x800000) /* Filter FIFO Assignment for Filter 23 */
  1945. #define CAN_FAFIFOR_FFA24 ((uint32_t)0x1000000) /* Filter FIFO Assignment for Filter 24 */
  1946. #define CAN_FAFIFOR_FFA25 ((uint32_t)0x2000000) /* Filter FIFO Assignment for Filter 25 */
  1947. #define CAN_FAFIFOR_FFA26 ((uint32_t)0x4000000) /* Filter FIFO Assignment for Filter 26 */
  1948. #define CAN_FAFIFOR_FFA27 ((uint32_t)0x8000000) /* Filter FIFO Assignment for Filter 27 */
  1949. /******************* Bit definition for CAN_FWR register *******************/
  1950. #define CAN_FWR_FACT ((uint16_t)0x3FFF) /* Filter Active */
  1951. #define CAN_FWR_FACT0 ((uint16_t)0x0001) /* Filter 0 Active */
  1952. #define CAN_FWR_FACT1 ((uint16_t)0x0002) /* Filter 1 Active */
  1953. #define CAN_FWR_FACT2 ((uint16_t)0x0004) /* Filter 2 Active */
  1954. #define CAN_FWR_FACT3 ((uint16_t)0x0008) /* Filter 3 Active */
  1955. #define CAN_FWR_FACT4 ((uint16_t)0x0010) /* Filter 4 Active */
  1956. #define CAN_FWR_FACT5 ((uint16_t)0x0020) /* Filter 5 Active */
  1957. #define CAN_FWR_FACT6 ((uint16_t)0x0040) /* Filter 6 Active */
  1958. #define CAN_FWR_FACT7 ((uint16_t)0x0080) /* Filter 7 Active */
  1959. #define CAN_FWR_FACT8 ((uint16_t)0x0100) /* Filter 8 Active */
  1960. #define CAN_FWR_FACT9 ((uint16_t)0x0200) /* Filter 9 Active */
  1961. #define CAN_FWR_FACT10 ((uint16_t)0x0400) /* Filter 10 Active */
  1962. #define CAN_FWR_FACT11 ((uint16_t)0x0800) /* Filter 11 Active */
  1963. #define CAN_FWR_FACT12 ((uint16_t)0x1000) /* Filter 12 Active */
  1964. #define CAN_FWR_FACT13 ((uint16_t)0x2000) /* Filter 13 Active */
  1965. #define CAN_FWR_FACT14 ((uint16_t)0x4000) /* Filter 14 Active */
  1966. #define CAN_FWR_FACT15 ((uint16_t)0x8000) /* Filter 15 Active */
  1967. #define CAN_FWR_FACT16 ((uint32_t)0x10000) /* Filter 16 Active */
  1968. #define CAN_FWR_FACT17 ((uint32_t)0x20000) /* Filter 17 Active */
  1969. #define CAN_FWR_FACT18 ((uint32_t)0x40000) /* Filter 18 Active */
  1970. #define CAN_FWR_FACT19 ((uint32_t)0x80000) /* Filter 19 Active */
  1971. #define CAN_FWR_FACT20 ((uint32_t)0x100000) /* Filter 20 Active */
  1972. #define CAN_FWR_FACT21 ((uint32_t)0x200000) /* Filter 21 Active */
  1973. #define CAN_FWR_FACT22 ((uint32_t)0x400000) /* Filter 22 Active */
  1974. #define CAN_FWR_FACT23 ((uint32_t)0x800000) /* Filter 23 Active */
  1975. #define CAN_FWR_FACT24 ((uint32_t)0x1000000) /* Filter 24 Active */
  1976. #define CAN_FWR_FACT25 ((uint32_t)0x2000000) /* Filter 25 Active */
  1977. #define CAN_FWR_FACT26 ((uint32_t)0x4000000) /* Filter 26 Active */
  1978. #define CAN_FWR_FACT27 ((uint32_t)0x8000000) /* Filter 27 Active */
  1979. /******************* Bit definition for CAN_F0R1 register *******************/
  1980. #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  1981. #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  1982. #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  1983. #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  1984. #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  1985. #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  1986. #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  1987. #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  1988. #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  1989. #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  1990. #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  1991. #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  1992. #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  1993. #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  1994. #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  1995. #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  1996. #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  1997. #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  1998. #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  1999. #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  2000. #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  2001. #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  2002. #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  2003. #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  2004. #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  2005. #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  2006. #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  2007. #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  2008. #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  2009. #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  2010. #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  2011. #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  2012. /******************* Bit definition for CAN_F1R1 register *******************/
  2013. #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  2014. #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  2015. #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  2016. #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  2017. #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  2018. #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  2019. #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  2020. #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  2021. #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  2022. #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  2023. #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  2024. #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  2025. #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  2026. #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  2027. #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  2028. #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  2029. #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  2030. #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  2031. #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  2032. #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  2033. #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  2034. #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  2035. #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  2036. #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  2037. #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  2038. #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  2039. #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  2040. #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  2041. #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  2042. #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  2043. #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  2044. #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  2045. /******************* Bit definition for CAN_F2R1 register *******************/
  2046. #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  2047. #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  2048. #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  2049. #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  2050. #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  2051. #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  2052. #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  2053. #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  2054. #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  2055. #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  2056. #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  2057. #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  2058. #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  2059. #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  2060. #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  2061. #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  2062. #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  2063. #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  2064. #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  2065. #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  2066. #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  2067. #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  2068. #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  2069. #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  2070. #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  2071. #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  2072. #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  2073. #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  2074. #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  2075. #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  2076. #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  2077. #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  2078. /******************* Bit definition for CAN_F3R1 register *******************/
  2079. #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  2080. #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  2081. #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  2082. #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  2083. #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  2084. #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  2085. #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  2086. #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  2087. #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  2088. #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  2089. #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  2090. #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  2091. #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  2092. #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  2093. #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  2094. #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  2095. #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  2096. #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  2097. #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  2098. #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  2099. #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  2100. #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  2101. #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  2102. #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  2103. #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  2104. #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  2105. #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  2106. #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  2107. #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  2108. #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  2109. #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  2110. #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  2111. /******************* Bit definition for CAN_F4R1 register *******************/
  2112. #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  2113. #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  2114. #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  2115. #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  2116. #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  2117. #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  2118. #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  2119. #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  2120. #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  2121. #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  2122. #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  2123. #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  2124. #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  2125. #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  2126. #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  2127. #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  2128. #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  2129. #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  2130. #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  2131. #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  2132. #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  2133. #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  2134. #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  2135. #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  2136. #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  2137. #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  2138. #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  2139. #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  2140. #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  2141. #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  2142. #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  2143. #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  2144. /******************* Bit definition for CAN_F5R1 register *******************/
  2145. #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  2146. #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  2147. #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  2148. #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  2149. #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  2150. #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  2151. #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  2152. #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  2153. #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  2154. #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  2155. #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  2156. #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  2157. #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  2158. #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  2159. #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  2160. #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  2161. #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  2162. #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  2163. #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  2164. #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  2165. #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  2166. #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  2167. #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  2168. #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  2169. #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  2170. #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  2171. #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  2172. #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  2173. #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  2174. #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  2175. #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  2176. #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  2177. /******************* Bit definition for CAN_F6R1 register *******************/
  2178. #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  2179. #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  2180. #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  2181. #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  2182. #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  2183. #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  2184. #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  2185. #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  2186. #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  2187. #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  2188. #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  2189. #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  2190. #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  2191. #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  2192. #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  2193. #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  2194. #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  2195. #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  2196. #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  2197. #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  2198. #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  2199. #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  2200. #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  2201. #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  2202. #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  2203. #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  2204. #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  2205. #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  2206. #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  2207. #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  2208. #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  2209. #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  2210. /******************* Bit definition for CAN_F7R1 register *******************/
  2211. #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  2212. #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  2213. #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  2214. #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  2215. #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  2216. #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  2217. #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  2218. #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  2219. #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  2220. #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  2221. #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  2222. #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  2223. #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  2224. #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  2225. #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  2226. #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  2227. #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  2228. #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  2229. #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  2230. #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  2231. #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  2232. #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  2233. #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  2234. #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  2235. #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  2236. #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  2237. #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  2238. #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  2239. #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  2240. #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  2241. #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  2242. #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  2243. /******************* Bit definition for CAN_F8R1 register *******************/
  2244. #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  2245. #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  2246. #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  2247. #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  2248. #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  2249. #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  2250. #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  2251. #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  2252. #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  2253. #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  2254. #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  2255. #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  2256. #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  2257. #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  2258. #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  2259. #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  2260. #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  2261. #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  2262. #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  2263. #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  2264. #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  2265. #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  2266. #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  2267. #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  2268. #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  2269. #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  2270. #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  2271. #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  2272. #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  2273. #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  2274. #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  2275. #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  2276. /******************* Bit definition for CAN_F9R1 register *******************/
  2277. #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  2278. #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  2279. #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  2280. #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  2281. #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  2282. #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  2283. #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  2284. #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  2285. #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  2286. #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  2287. #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  2288. #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  2289. #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  2290. #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  2291. #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  2292. #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  2293. #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  2294. #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  2295. #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  2296. #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  2297. #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  2298. #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  2299. #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  2300. #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  2301. #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  2302. #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  2303. #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  2304. #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  2305. #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  2306. #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  2307. #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  2308. #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  2309. /******************* Bit definition for CAN_F10R1 register ******************/
  2310. #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  2311. #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  2312. #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  2313. #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  2314. #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  2315. #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  2316. #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  2317. #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  2318. #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  2319. #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  2320. #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  2321. #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  2322. #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  2323. #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  2324. #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  2325. #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  2326. #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  2327. #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  2328. #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  2329. #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  2330. #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  2331. #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  2332. #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  2333. #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  2334. #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  2335. #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  2336. #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  2337. #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  2338. #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  2339. #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  2340. #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  2341. #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  2342. /******************* Bit definition for CAN_F11R1 register ******************/
  2343. #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  2344. #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  2345. #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  2346. #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  2347. #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  2348. #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  2349. #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  2350. #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  2351. #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  2352. #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  2353. #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  2354. #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  2355. #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  2356. #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  2357. #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  2358. #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  2359. #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  2360. #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  2361. #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  2362. #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  2363. #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  2364. #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  2365. #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  2366. #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  2367. #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  2368. #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  2369. #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  2370. #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  2371. #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  2372. #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  2373. #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  2374. #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  2375. /******************* Bit definition for CAN_F12R1 register ******************/
  2376. #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  2377. #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  2378. #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  2379. #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  2380. #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  2381. #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  2382. #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  2383. #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  2384. #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  2385. #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  2386. #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  2387. #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  2388. #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  2389. #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  2390. #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  2391. #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  2392. #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  2393. #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  2394. #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  2395. #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  2396. #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  2397. #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  2398. #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  2399. #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  2400. #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  2401. #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  2402. #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  2403. #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  2404. #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  2405. #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  2406. #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  2407. #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  2408. /******************* Bit definition for CAN_F13R1 register ******************/
  2409. #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  2410. #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  2411. #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  2412. #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  2413. #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  2414. #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  2415. #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  2416. #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  2417. #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  2418. #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  2419. #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  2420. #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  2421. #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  2422. #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  2423. #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  2424. #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  2425. #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  2426. #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  2427. #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  2428. #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  2429. #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  2430. #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  2431. #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  2432. #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  2433. #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  2434. #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  2435. #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  2436. #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  2437. #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  2438. #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  2439. #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  2440. #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  2441. /******************* Bit definition for CAN_F14R1 register ******************/
  2442. #define CAN_F14R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  2443. #define CAN_F14R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  2444. #define CAN_F14R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  2445. #define CAN_F14R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  2446. #define CAN_F14R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  2447. #define CAN_F14R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  2448. #define CAN_F14R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  2449. #define CAN_F14R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  2450. #define CAN_F14R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  2451. #define CAN_F14R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  2452. #define CAN_F14R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  2453. #define CAN_F14R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  2454. #define CAN_F14R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  2455. #define CAN_F14R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  2456. #define CAN_F14R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  2457. #define CAN_F14R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  2458. #define CAN_F14R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  2459. #define CAN_F14R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  2460. #define CAN_F14R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  2461. #define CAN_F14R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  2462. #define CAN_F14R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  2463. #define CAN_F14R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  2464. #define CAN_F14R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  2465. #define CAN_F14R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  2466. #define CAN_F14R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  2467. #define CAN_F14R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  2468. #define CAN_F14R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  2469. #define CAN_F14R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  2470. #define CAN_F14R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  2471. #define CAN_F14R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  2472. #define CAN_F14R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  2473. #define CAN_F14R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  2474. /******************* Bit definition for CAN_F15R1 register *******************/
  2475. #define CAN_F15R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  2476. #define CAN_F15R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  2477. #define CAN_F15R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  2478. #define CAN_F15R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  2479. #define CAN_F15R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  2480. #define CAN_F15R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  2481. #define CAN_F15R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  2482. #define CAN_F15R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  2483. #define CAN_F15R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  2484. #define CAN_F15R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  2485. #define CAN_F15R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  2486. #define CAN_F15R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  2487. #define CAN_F15R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  2488. #define CAN_F15R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  2489. #define CAN_F15R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  2490. #define CAN_F15R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  2491. #define CAN_F15R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  2492. #define CAN_F15R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  2493. #define CAN_F15R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  2494. #define CAN_F15R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  2495. #define CAN_F15R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  2496. #define CAN_F15R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  2497. #define CAN_F15R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  2498. #define CAN_F15R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  2499. #define CAN_F15R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  2500. #define CAN_F15R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  2501. #define CAN_F15R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  2502. #define CAN_F15R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  2503. #define CAN_F15R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  2504. #define CAN_F15R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  2505. #define CAN_F15R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  2506. #define CAN_F15R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  2507. /******************* Bit definition for CAN_F16R1 register *******************/
  2508. #define CAN_F16R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  2509. #define CAN_F16R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  2510. #define CAN_F16R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  2511. #define CAN_F16R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  2512. #define CAN_F16R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  2513. #define CAN_F16R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  2514. #define CAN_F16R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  2515. #define CAN_F16R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  2516. #define CAN_F16R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  2517. #define CAN_F16R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  2518. #define CAN_F16R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  2519. #define CAN_F16R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  2520. #define CAN_F16R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  2521. #define CAN_F16R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  2522. #define CAN_F16R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  2523. #define CAN_F16R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  2524. #define CAN_F16R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  2525. #define CAN_F16R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  2526. #define CAN_F16R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  2527. #define CAN_F16R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  2528. #define CAN_F16R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  2529. #define CAN_F16R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  2530. #define CAN_F16R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  2531. #define CAN_F16R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  2532. #define CAN_F16R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  2533. #define CAN_F16R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  2534. #define CAN_F16R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  2535. #define CAN_F16R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  2536. #define CAN_F16R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  2537. #define CAN_F16R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  2538. #define CAN_F16R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  2539. #define CAN_F16R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  2540. /******************* Bit definition for CAN_F17R1 register *******************/
  2541. #define CAN_F17R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  2542. #define CAN_F17R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  2543. #define CAN_F17R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  2544. #define CAN_F17R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  2545. #define CAN_F17R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  2546. #define CAN_F17R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  2547. #define CAN_F17R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  2548. #define CAN_F17R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  2549. #define CAN_F17R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  2550. #define CAN_F17R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  2551. #define CAN_F17R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  2552. #define CAN_F17R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  2553. #define CAN_F17R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  2554. #define CAN_F17R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  2555. #define CAN_F17R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  2556. #define CAN_F17R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  2557. #define CAN_F17R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  2558. #define CAN_F17R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  2559. #define CAN_F17R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  2560. #define CAN_F17R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  2561. #define CAN_F17R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  2562. #define CAN_F17R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  2563. #define CAN_F17R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  2564. #define CAN_F17R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  2565. #define CAN_F17R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  2566. #define CAN_F17R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  2567. #define CAN_F17R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  2568. #define CAN_F17R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  2569. #define CAN_F17R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  2570. #define CAN_F17R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  2571. #define CAN_F17R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  2572. #define CAN_F17R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  2573. /******************* Bit definition for CAN_F18R1 register *******************/
  2574. #define CAN_F18R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  2575. #define CAN_F18R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  2576. #define CAN_F18R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  2577. #define CAN_F18R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  2578. #define CAN_F18R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  2579. #define CAN_F18R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  2580. #define CAN_F18R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  2581. #define CAN_F18R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  2582. #define CAN_F18R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  2583. #define CAN_F18R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  2584. #define CAN_F18R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  2585. #define CAN_F18R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  2586. #define CAN_F18R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  2587. #define CAN_F18R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  2588. #define CAN_F18R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  2589. #define CAN_F18R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  2590. #define CAN_F18R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  2591. #define CAN_F18R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  2592. #define CAN_F18R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  2593. #define CAN_F18R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  2594. #define CAN_F18R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  2595. #define CAN_F18R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  2596. #define CAN_F18R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  2597. #define CAN_F18R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  2598. #define CAN_F18R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  2599. #define CAN_F18R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  2600. #define CAN_F18R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  2601. #define CAN_F18R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  2602. #define CAN_F18R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  2603. #define CAN_F18R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  2604. #define CAN_F18R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  2605. #define CAN_F18R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  2606. /******************* Bit definition for CAN_F19R1 register *******************/
  2607. #define CAN_F19R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  2608. #define CAN_F19R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  2609. #define CAN_F19R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  2610. #define CAN_F19R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  2611. #define CAN_F19R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  2612. #define CAN_F19R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  2613. #define CAN_F19R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  2614. #define CAN_F19R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  2615. #define CAN_F19R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  2616. #define CAN_F19R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  2617. #define CAN_F19R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  2618. #define CAN_F19R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  2619. #define CAN_F19R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  2620. #define CAN_F19R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  2621. #define CAN_F19R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  2622. #define CAN_F19R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  2623. #define CAN_F19R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  2624. #define CAN_F19R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  2625. #define CAN_F19R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  2626. #define CAN_F19R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  2627. #define CAN_F19R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  2628. #define CAN_F19R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  2629. #define CAN_F19R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  2630. #define CAN_F19R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  2631. #define CAN_F19R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  2632. #define CAN_F19R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  2633. #define CAN_F19R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  2634. #define CAN_F19R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  2635. #define CAN_F19R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  2636. #define CAN_F19R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  2637. #define CAN_F19R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  2638. #define CAN_F19R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  2639. /******************* Bit definition for CAN_F20R1 register *******************/
  2640. #define CAN_F20R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  2641. #define CAN_F20R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  2642. #define CAN_F20R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  2643. #define CAN_F20R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  2644. #define CAN_F20R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  2645. #define CAN_F20R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  2646. #define CAN_F20R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  2647. #define CAN_F20R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  2648. #define CAN_F20R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  2649. #define CAN_F20R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  2650. #define CAN_F20R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  2651. #define CAN_F20R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  2652. #define CAN_F20R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  2653. #define CAN_F20R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  2654. #define CAN_F20R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  2655. #define CAN_F20R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  2656. #define CAN_F20R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  2657. #define CAN_F20R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  2658. #define CAN_F20R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  2659. #define CAN_F20R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  2660. #define CAN_F20R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  2661. #define CAN_F20R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  2662. #define CAN_F20R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  2663. #define CAN_F20R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  2664. #define CAN_F20R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  2665. #define CAN_F20R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  2666. #define CAN_F20R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  2667. #define CAN_F20R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  2668. #define CAN_F20R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  2669. #define CAN_F20R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  2670. #define CAN_F20R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  2671. #define CAN_F20R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  2672. /******************* Bit definition for CAN_F21R1 register *******************/
  2673. #define CAN_F21R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  2674. #define CAN_F21R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  2675. #define CAN_F21R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  2676. #define CAN_F21R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  2677. #define CAN_F21R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  2678. #define CAN_F21R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  2679. #define CAN_F21R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  2680. #define CAN_F21R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  2681. #define CAN_F21R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  2682. #define CAN_F21R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  2683. #define CAN_F21R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  2684. #define CAN_F21R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  2685. #define CAN_F21R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  2686. #define CAN_F21R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  2687. #define CAN_F21R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  2688. #define CAN_F21R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  2689. #define CAN_F21R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  2690. #define CAN_F21R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  2691. #define CAN_F21R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  2692. #define CAN_F21R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  2693. #define CAN_F21R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  2694. #define CAN_F21R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  2695. #define CAN_F21R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  2696. #define CAN_F21R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  2697. #define CAN_F21R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  2698. #define CAN_F21R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  2699. #define CAN_F21R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  2700. #define CAN_F21R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  2701. #define CAN_F21R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  2702. #define CAN_F21R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  2703. #define CAN_F21R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  2704. #define CAN_F21R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  2705. /******************* Bit definition for CAN_F22R1 register *******************/
  2706. #define CAN_F22R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  2707. #define CAN_F22R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  2708. #define CAN_F22R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  2709. #define CAN_F22R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  2710. #define CAN_F22R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  2711. #define CAN_F22R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  2712. #define CAN_F22R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  2713. #define CAN_F22R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  2714. #define CAN_F22R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  2715. #define CAN_F22R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  2716. #define CAN_F22R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  2717. #define CAN_F22R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  2718. #define CAN_F22R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  2719. #define CAN_F22R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  2720. #define CAN_F22R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  2721. #define CAN_F22R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  2722. #define CAN_F22R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  2723. #define CAN_F22R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  2724. #define CAN_F22R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  2725. #define CAN_F22R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  2726. #define CAN_F22R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  2727. #define CAN_F22R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  2728. #define CAN_F22R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  2729. #define CAN_F22R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  2730. #define CAN_F22R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  2731. #define CAN_F22R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  2732. #define CAN_F22R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  2733. #define CAN_F22R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  2734. #define CAN_F22R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  2735. #define CAN_F22R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  2736. #define CAN_F22R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  2737. #define CAN_F22R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  2738. /******************* Bit definition for CAN_F23R1 register ******************/
  2739. #define CAN_F23R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  2740. #define CAN_F23R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  2741. #define CAN_F23R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  2742. #define CAN_F23R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  2743. #define CAN_F23R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  2744. #define CAN_F23R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  2745. #define CAN_F23R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  2746. #define CAN_F23R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  2747. #define CAN_F23R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  2748. #define CAN_F23R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  2749. #define CAN_F23R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  2750. #define CAN_F23R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  2751. #define CAN_F23R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  2752. #define CAN_F23R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  2753. #define CAN_F23R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  2754. #define CAN_F23R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  2755. #define CAN_F23R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  2756. #define CAN_F23R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  2757. #define CAN_F23R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  2758. #define CAN_F23R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  2759. #define CAN_F23R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  2760. #define CAN_F23R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  2761. #define CAN_F23R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  2762. #define CAN_F23R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  2763. #define CAN_F23R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  2764. #define CAN_F23R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  2765. #define CAN_F23R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  2766. #define CAN_F23R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  2767. #define CAN_F23R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  2768. #define CAN_F23R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  2769. #define CAN_F23R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  2770. #define CAN_F23R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  2771. /******************* Bit definition for CAN_F24R1 register ******************/
  2772. #define CAN_F24R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  2773. #define CAN_F24R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  2774. #define CAN_F24R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  2775. #define CAN_F24R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  2776. #define CAN_F24R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  2777. #define CAN_F24R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  2778. #define CAN_F24R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  2779. #define CAN_F24R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  2780. #define CAN_F24R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  2781. #define CAN_F24R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  2782. #define CAN_F24R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  2783. #define CAN_F24R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  2784. #define CAN_F24R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  2785. #define CAN_F24R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  2786. #define CAN_F24R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  2787. #define CAN_F24R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  2788. #define CAN_F24R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  2789. #define CAN_F24R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  2790. #define CAN_F24R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  2791. #define CAN_F24R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  2792. #define CAN_F24R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  2793. #define CAN_F24R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  2794. #define CAN_F24R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  2795. #define CAN_F24R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  2796. #define CAN_F24R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  2797. #define CAN_F24R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  2798. #define CAN_F24R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  2799. #define CAN_F24R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  2800. #define CAN_F24R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  2801. #define CAN_F24R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  2802. #define CAN_F24R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  2803. #define CAN_F24R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  2804. /******************* Bit definition for CAN_F25R1 register ******************/
  2805. #define CAN_F25R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  2806. #define CAN_F25R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  2807. #define CAN_F25R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  2808. #define CAN_F25R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  2809. #define CAN_F25R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  2810. #define CAN_F25R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  2811. #define CAN_F25R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  2812. #define CAN_F25R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  2813. #define CAN_F25R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  2814. #define CAN_F25R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  2815. #define CAN_F25R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  2816. #define CAN_F25R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  2817. #define CAN_F25R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  2818. #define CAN_F25R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  2819. #define CAN_F25R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  2820. #define CAN_F25R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  2821. #define CAN_F25R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  2822. #define CAN_F25R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  2823. #define CAN_F25R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  2824. #define CAN_F25R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  2825. #define CAN_F25R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  2826. #define CAN_F25R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  2827. #define CAN_F25R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  2828. #define CAN_F25R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  2829. #define CAN_F25R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  2830. #define CAN_F25R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  2831. #define CAN_F25R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  2832. #define CAN_F25R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  2833. #define CAN_F25R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  2834. #define CAN_F25R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  2835. #define CAN_F25R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  2836. #define CAN_F25R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  2837. /******************* Bit definition for CAN_F26R1 register ******************/
  2838. #define CAN_F26R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  2839. #define CAN_F26R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  2840. #define CAN_F26R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  2841. #define CAN_F26R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  2842. #define CAN_F26R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  2843. #define CAN_F26R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  2844. #define CAN_F26R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  2845. #define CAN_F26R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  2846. #define CAN_F26R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  2847. #define CAN_F26R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  2848. #define CAN_F26R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  2849. #define CAN_F26R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  2850. #define CAN_F26R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  2851. #define CAN_F26R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  2852. #define CAN_F26R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  2853. #define CAN_F26R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  2854. #define CAN_F26R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  2855. #define CAN_F26R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  2856. #define CAN_F26R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  2857. #define CAN_F26R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  2858. #define CAN_F26R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  2859. #define CAN_F26R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  2860. #define CAN_F26R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  2861. #define CAN_F26R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  2862. #define CAN_F26R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  2863. #define CAN_F26R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  2864. #define CAN_F26R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  2865. #define CAN_F26R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  2866. #define CAN_F26R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  2867. #define CAN_F26R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  2868. #define CAN_F26R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  2869. #define CAN_F26R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  2870. /******************* Bit definition for CAN_F27R1 register ******************/
  2871. #define CAN_F27R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  2872. #define CAN_F27R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  2873. #define CAN_F27R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  2874. #define CAN_F27R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  2875. #define CAN_F27R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  2876. #define CAN_F27R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  2877. #define CAN_F27R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  2878. #define CAN_F27R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  2879. #define CAN_F27R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  2880. #define CAN_F27R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  2881. #define CAN_F27R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  2882. #define CAN_F27R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  2883. #define CAN_F27R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  2884. #define CAN_F27R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  2885. #define CAN_F27R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  2886. #define CAN_F27R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  2887. #define CAN_F27R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  2888. #define CAN_F27R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  2889. #define CAN_F27R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  2890. #define CAN_F27R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  2891. #define CAN_F27R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  2892. #define CAN_F27R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  2893. #define CAN_F27R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  2894. #define CAN_F27R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  2895. #define CAN_F27R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  2896. #define CAN_F27R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  2897. #define CAN_F27R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  2898. #define CAN_F27R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  2899. #define CAN_F27R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  2900. #define CAN_F27R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  2901. #define CAN_F27R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  2902. #define CAN_F27R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  2903. /******************* Bit definition for CAN_F0R2 register *******************/
  2904. #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  2905. #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  2906. #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  2907. #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  2908. #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  2909. #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  2910. #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  2911. #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  2912. #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  2913. #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  2914. #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  2915. #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  2916. #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  2917. #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  2918. #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  2919. #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  2920. #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  2921. #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  2922. #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  2923. #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  2924. #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  2925. #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  2926. #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  2927. #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  2928. #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  2929. #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  2930. #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  2931. #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  2932. #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  2933. #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  2934. #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  2935. #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  2936. /******************* Bit definition for CAN_F1R2 register *******************/
  2937. #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  2938. #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  2939. #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  2940. #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  2941. #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  2942. #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  2943. #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  2944. #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  2945. #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  2946. #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  2947. #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  2948. #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  2949. #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  2950. #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  2951. #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  2952. #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  2953. #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  2954. #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  2955. #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  2956. #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  2957. #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  2958. #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  2959. #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  2960. #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  2961. #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  2962. #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  2963. #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  2964. #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  2965. #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  2966. #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  2967. #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  2968. #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  2969. /******************* Bit definition for CAN_F2R2 register *******************/
  2970. #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  2971. #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  2972. #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  2973. #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  2974. #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  2975. #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  2976. #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  2977. #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  2978. #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  2979. #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  2980. #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  2981. #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  2982. #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  2983. #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  2984. #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  2985. #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  2986. #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  2987. #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  2988. #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  2989. #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  2990. #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  2991. #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  2992. #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  2993. #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  2994. #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  2995. #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  2996. #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  2997. #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  2998. #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  2999. #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  3000. #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  3001. #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  3002. /******************* Bit definition for CAN_F3R2 register *******************/
  3003. #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  3004. #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  3005. #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  3006. #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  3007. #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  3008. #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  3009. #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  3010. #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  3011. #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  3012. #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  3013. #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  3014. #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  3015. #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  3016. #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  3017. #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  3018. #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  3019. #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  3020. #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  3021. #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  3022. #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  3023. #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  3024. #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  3025. #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  3026. #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  3027. #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  3028. #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  3029. #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  3030. #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  3031. #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  3032. #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  3033. #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  3034. #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  3035. /******************* Bit definition for CAN_F4R2 register *******************/
  3036. #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  3037. #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  3038. #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  3039. #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  3040. #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  3041. #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  3042. #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  3043. #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  3044. #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  3045. #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  3046. #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  3047. #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  3048. #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  3049. #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  3050. #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  3051. #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  3052. #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  3053. #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  3054. #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  3055. #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  3056. #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  3057. #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  3058. #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  3059. #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  3060. #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  3061. #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  3062. #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  3063. #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  3064. #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  3065. #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  3066. #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  3067. #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  3068. /******************* Bit definition for CAN_F5R2 register *******************/
  3069. #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  3070. #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  3071. #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  3072. #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  3073. #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  3074. #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  3075. #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  3076. #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  3077. #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  3078. #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  3079. #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  3080. #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  3081. #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  3082. #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  3083. #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  3084. #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  3085. #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  3086. #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  3087. #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  3088. #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  3089. #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  3090. #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  3091. #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  3092. #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  3093. #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  3094. #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  3095. #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  3096. #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  3097. #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  3098. #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  3099. #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  3100. #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  3101. /******************* Bit definition for CAN_F6R2 register *******************/
  3102. #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  3103. #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  3104. #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  3105. #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  3106. #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  3107. #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  3108. #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  3109. #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  3110. #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  3111. #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  3112. #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  3113. #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  3114. #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  3115. #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  3116. #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  3117. #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  3118. #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  3119. #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  3120. #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  3121. #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  3122. #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  3123. #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  3124. #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  3125. #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  3126. #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  3127. #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  3128. #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  3129. #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  3130. #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  3131. #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  3132. #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  3133. #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  3134. /******************* Bit definition for CAN_F7R2 register *******************/
  3135. #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  3136. #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  3137. #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  3138. #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  3139. #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  3140. #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  3141. #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  3142. #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  3143. #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  3144. #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  3145. #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  3146. #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  3147. #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  3148. #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  3149. #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  3150. #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  3151. #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  3152. #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  3153. #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  3154. #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  3155. #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  3156. #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  3157. #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  3158. #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  3159. #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  3160. #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  3161. #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  3162. #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  3163. #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  3164. #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  3165. #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  3166. #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  3167. /******************* Bit definition for CAN_F8R2 register *******************/
  3168. #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  3169. #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  3170. #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  3171. #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  3172. #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  3173. #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  3174. #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  3175. #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  3176. #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  3177. #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  3178. #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  3179. #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  3180. #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  3181. #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  3182. #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  3183. #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  3184. #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  3185. #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  3186. #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  3187. #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  3188. #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  3189. #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  3190. #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  3191. #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  3192. #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  3193. #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  3194. #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  3195. #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  3196. #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  3197. #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  3198. #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  3199. #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  3200. /******************* Bit definition for CAN_F9R2 register *******************/
  3201. #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  3202. #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  3203. #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  3204. #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  3205. #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  3206. #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  3207. #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  3208. #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  3209. #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  3210. #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  3211. #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  3212. #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  3213. #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  3214. #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  3215. #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  3216. #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  3217. #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  3218. #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  3219. #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  3220. #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  3221. #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  3222. #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  3223. #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  3224. #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  3225. #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  3226. #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  3227. #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  3228. #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  3229. #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  3230. #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  3231. #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  3232. #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  3233. /******************* Bit definition for CAN_F10R2 register ******************/
  3234. #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  3235. #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  3236. #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  3237. #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  3238. #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  3239. #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  3240. #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  3241. #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  3242. #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  3243. #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  3244. #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  3245. #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  3246. #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  3247. #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  3248. #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  3249. #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  3250. #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  3251. #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  3252. #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  3253. #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  3254. #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  3255. #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  3256. #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  3257. #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  3258. #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  3259. #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  3260. #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  3261. #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  3262. #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  3263. #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  3264. #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  3265. #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  3266. /******************* Bit definition for CAN_F11R2 register ******************/
  3267. #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  3268. #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  3269. #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  3270. #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  3271. #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  3272. #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  3273. #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  3274. #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  3275. #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  3276. #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  3277. #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  3278. #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  3279. #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  3280. #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  3281. #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  3282. #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  3283. #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  3284. #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  3285. #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  3286. #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  3287. #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  3288. #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  3289. #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  3290. #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  3291. #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  3292. #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  3293. #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  3294. #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  3295. #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  3296. #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  3297. #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  3298. #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  3299. /******************* Bit definition for CAN_F12R2 register ******************/
  3300. #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  3301. #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  3302. #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  3303. #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  3304. #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  3305. #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  3306. #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  3307. #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  3308. #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  3309. #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  3310. #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  3311. #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  3312. #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  3313. #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  3314. #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  3315. #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  3316. #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  3317. #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  3318. #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  3319. #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  3320. #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  3321. #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  3322. #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  3323. #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  3324. #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  3325. #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  3326. #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  3327. #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  3328. #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  3329. #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  3330. #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  3331. #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  3332. /******************* Bit definition for CAN_F13R2 register ******************/
  3333. #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  3334. #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  3335. #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  3336. #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  3337. #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  3338. #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  3339. #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  3340. #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  3341. #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  3342. #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  3343. #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  3344. #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  3345. #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  3346. #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  3347. #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  3348. #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  3349. #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  3350. #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  3351. #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  3352. #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  3353. #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  3354. #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  3355. #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  3356. #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  3357. #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  3358. #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  3359. #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  3360. #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  3361. #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  3362. #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  3363. #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  3364. #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  3365. /******************* Bit definition for CAN_F14R2 register *******************/
  3366. #define CAN_F14R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  3367. #define CAN_F14R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  3368. #define CAN_F14R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  3369. #define CAN_F14R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  3370. #define CAN_F14R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  3371. #define CAN_F14R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  3372. #define CAN_F14R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  3373. #define CAN_F14R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  3374. #define CAN_F14R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  3375. #define CAN_F14R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  3376. #define CAN_F14R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  3377. #define CAN_F14R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  3378. #define CAN_F14R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  3379. #define CAN_F14R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  3380. #define CAN_F14R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  3381. #define CAN_F14R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  3382. #define CAN_F14R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  3383. #define CAN_F14R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  3384. #define CAN_F14R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  3385. #define CAN_F14R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  3386. #define CAN_F14R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  3387. #define CAN_F14R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  3388. #define CAN_F14R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  3389. #define CAN_F14R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  3390. #define CAN_F14R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  3391. #define CAN_F14R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  3392. #define CAN_F14R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  3393. #define CAN_F14R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  3394. #define CAN_F14R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  3395. #define CAN_F14R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  3396. #define CAN_F14R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  3397. #define CAN_F14R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  3398. /******************* Bit definition for CAN_F15R2 register *******************/
  3399. #define CAN_F15R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  3400. #define CAN_F15R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  3401. #define CAN_F15R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  3402. #define CAN_F15R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  3403. #define CAN_F15R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  3404. #define CAN_F15R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  3405. #define CAN_F15R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  3406. #define CAN_F15R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  3407. #define CAN_F15R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  3408. #define CAN_F15R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  3409. #define CAN_F15R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  3410. #define CAN_F15R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  3411. #define CAN_F15R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  3412. #define CAN_F15R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  3413. #define CAN_F15R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  3414. #define CAN_F15R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  3415. #define CAN_F15R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  3416. #define CAN_F15R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  3417. #define CAN_F15R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  3418. #define CAN_F15R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  3419. #define CAN_F15R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  3420. #define CAN_F15R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  3421. #define CAN_F15R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  3422. #define CAN_F15R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  3423. #define CAN_F15R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  3424. #define CAN_F15R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  3425. #define CAN_F15R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  3426. #define CAN_F15R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  3427. #define CAN_F15R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  3428. #define CAN_F15R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  3429. #define CAN_F15R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  3430. #define CAN_F15R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  3431. /******************* Bit definition for CAN_F16R2 register *******************/
  3432. #define CAN_F16R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  3433. #define CAN_F16R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  3434. #define CAN_F16R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  3435. #define CAN_F16R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  3436. #define CAN_F16R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  3437. #define CAN_F16R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  3438. #define CAN_F16R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  3439. #define CAN_F16R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  3440. #define CAN_F16R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  3441. #define CAN_F16R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  3442. #define CAN_F16R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  3443. #define CAN_F16R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  3444. #define CAN_F16R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  3445. #define CAN_F16R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  3446. #define CAN_F16R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  3447. #define CAN_F16R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  3448. #define CAN_F16R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  3449. #define CAN_F16R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  3450. #define CAN_F16R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  3451. #define CAN_F16R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  3452. #define CAN_F16R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  3453. #define CAN_F16R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  3454. #define CAN_F16R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  3455. #define CAN_F16R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  3456. #define CAN_F16R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  3457. #define CAN_F16R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  3458. #define CAN_F16R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  3459. #define CAN_F16R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  3460. #define CAN_F16R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  3461. #define CAN_F16R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  3462. #define CAN_F16R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  3463. #define CAN_F16R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  3464. /******************* Bit definition for CAN_F17R2 register *******************/
  3465. #define CAN_F17R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  3466. #define CAN_F17R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  3467. #define CAN_F17R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  3468. #define CAN_F17R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  3469. #define CAN_F17R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  3470. #define CAN_F17R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  3471. #define CAN_F17R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  3472. #define CAN_F17R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  3473. #define CAN_F17R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  3474. #define CAN_F17R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  3475. #define CAN_F17R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  3476. #define CAN_F17R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  3477. #define CAN_F17R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  3478. #define CAN_F17R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  3479. #define CAN_F17R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  3480. #define CAN_F17R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  3481. #define CAN_F17R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  3482. #define CAN_F17R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  3483. #define CAN_F17R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  3484. #define CAN_F17R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  3485. #define CAN_F17R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  3486. #define CAN_F17R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  3487. #define CAN_F17R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  3488. #define CAN_F17R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  3489. #define CAN_F17R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  3490. #define CAN_F17R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  3491. #define CAN_F17R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  3492. #define CAN_F17R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  3493. #define CAN_F17R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  3494. #define CAN_F17R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  3495. #define CAN_F17R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  3496. #define CAN_F17R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  3497. /******************* Bit definition for CAN_F18R2 register *******************/
  3498. #define CAN_F18R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  3499. #define CAN_F18R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  3500. #define CAN_F18R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  3501. #define CAN_F18R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  3502. #define CAN_F18R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  3503. #define CAN_F18R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  3504. #define CAN_F18R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  3505. #define CAN_F18R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  3506. #define CAN_F18R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  3507. #define CAN_F18R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  3508. #define CAN_F18R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  3509. #define CAN_F18R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  3510. #define CAN_F18R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  3511. #define CAN_F18R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  3512. #define CAN_F18R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  3513. #define CAN_F18R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  3514. #define CAN_F18R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  3515. #define CAN_F18R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  3516. #define CAN_F18R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  3517. #define CAN_F18R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  3518. #define CAN_F18R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  3519. #define CAN_F18R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  3520. #define CAN_F18R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  3521. #define CAN_F18R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  3522. #define CAN_F18R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  3523. #define CAN_F18R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  3524. #define CAN_F18R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  3525. #define CAN_F18R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  3526. #define CAN_F18R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  3527. #define CAN_F18R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  3528. #define CAN_F18R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  3529. #define CAN_F18R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  3530. /******************* Bit definition for CAN_F19R2 register *******************/
  3531. #define CAN_F19R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  3532. #define CAN_F19R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  3533. #define CAN_F19R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  3534. #define CAN_F19R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  3535. #define CAN_F19R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  3536. #define CAN_F19R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  3537. #define CAN_F19R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  3538. #define CAN_F19R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  3539. #define CAN_F19R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  3540. #define CAN_F19R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  3541. #define CAN_F19R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  3542. #define CAN_F19R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  3543. #define CAN_F19R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  3544. #define CAN_F19R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  3545. #define CAN_F19R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  3546. #define CAN_F19R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  3547. #define CAN_F19R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  3548. #define CAN_F19R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  3549. #define CAN_F19R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  3550. #define CAN_F19R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  3551. #define CAN_F19R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  3552. #define CAN_F19R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  3553. #define CAN_F19R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  3554. #define CAN_F19R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  3555. #define CAN_F19R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  3556. #define CAN_F19R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  3557. #define CAN_F19R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  3558. #define CAN_F19R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  3559. #define CAN_F19R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  3560. #define CAN_F19R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  3561. #define CAN_F19R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  3562. #define CAN_F19R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  3563. /******************* Bit definition for CAN_F20R2 register *******************/
  3564. #define CAN_F20R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  3565. #define CAN_F20R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  3566. #define CAN_F20R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  3567. #define CAN_F20R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  3568. #define CAN_F20R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  3569. #define CAN_F20R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  3570. #define CAN_F20R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  3571. #define CAN_F20R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  3572. #define CAN_F20R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  3573. #define CAN_F20R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  3574. #define CAN_F20R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  3575. #define CAN_F20R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  3576. #define CAN_F20R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  3577. #define CAN_F20R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  3578. #define CAN_F20R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  3579. #define CAN_F20R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  3580. #define CAN_F20R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  3581. #define CAN_F20R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  3582. #define CAN_F20R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  3583. #define CAN_F20R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  3584. #define CAN_F20R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  3585. #define CAN_F20R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  3586. #define CAN_F20R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  3587. #define CAN_F20R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  3588. #define CAN_F20R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  3589. #define CAN_F20R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  3590. #define CAN_F20R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  3591. #define CAN_F20R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  3592. #define CAN_F20R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  3593. #define CAN_F20R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  3594. #define CAN_F20R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  3595. #define CAN_F20R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  3596. /******************* Bit definition for CAN_F21R2 register *******************/
  3597. #define CAN_F21R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  3598. #define CAN_F21R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  3599. #define CAN_F21R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  3600. #define CAN_F21R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  3601. #define CAN_F21R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  3602. #define CAN_F21R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  3603. #define CAN_F21R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  3604. #define CAN_F21R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  3605. #define CAN_F21R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  3606. #define CAN_F21R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  3607. #define CAN_F21R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  3608. #define CAN_F21R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  3609. #define CAN_F21R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  3610. #define CAN_F21R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  3611. #define CAN_F21R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  3612. #define CAN_F21R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  3613. #define CAN_F21R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  3614. #define CAN_F21R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  3615. #define CAN_F21R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  3616. #define CAN_F21R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  3617. #define CAN_F21R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  3618. #define CAN_F21R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  3619. #define CAN_F21R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  3620. #define CAN_F21R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  3621. #define CAN_F21R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  3622. #define CAN_F21R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  3623. #define CAN_F21R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  3624. #define CAN_F21R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  3625. #define CAN_F21R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  3626. #define CAN_F21R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  3627. #define CAN_F21R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  3628. #define CAN_F21R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  3629. /******************* Bit definition for CAN_F22R2 register *******************/
  3630. #define CAN_F22R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  3631. #define CAN_F22R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  3632. #define CAN_F22R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  3633. #define CAN_F22R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  3634. #define CAN_F22R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  3635. #define CAN_F22R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  3636. #define CAN_F22R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  3637. #define CAN_F22R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  3638. #define CAN_F22R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  3639. #define CAN_F22R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  3640. #define CAN_F22R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  3641. #define CAN_F22R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  3642. #define CAN_F22R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  3643. #define CAN_F22R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  3644. #define CAN_F22R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  3645. #define CAN_F22R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  3646. #define CAN_F22R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  3647. #define CAN_F22R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  3648. #define CAN_F22R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  3649. #define CAN_F22R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  3650. #define CAN_F22R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  3651. #define CAN_F22R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  3652. #define CAN_F22R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  3653. #define CAN_F22R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  3654. #define CAN_F22R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  3655. #define CAN_F22R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  3656. #define CAN_F22R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  3657. #define CAN_F22R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  3658. #define CAN_F22R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  3659. #define CAN_F22R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  3660. #define CAN_F22R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  3661. #define CAN_F22R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  3662. /******************* Bit definition for CAN_F23R2 register *******************/
  3663. #define CAN_F23R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  3664. #define CAN_F23R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  3665. #define CAN_F23R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  3666. #define CAN_F23R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  3667. #define CAN_F23R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  3668. #define CAN_F23R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  3669. #define CAN_F23R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  3670. #define CAN_F23R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  3671. #define CAN_F23R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  3672. #define CAN_F23R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  3673. #define CAN_F23R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  3674. #define CAN_F23R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  3675. #define CAN_F23R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  3676. #define CAN_F23R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  3677. #define CAN_F23R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  3678. #define CAN_F23R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  3679. #define CAN_F23R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  3680. #define CAN_F23R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  3681. #define CAN_F23R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  3682. #define CAN_F23R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  3683. #define CAN_F23R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  3684. #define CAN_F23R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  3685. #define CAN_F23R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  3686. #define CAN_F23R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  3687. #define CAN_F23R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  3688. #define CAN_F23R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  3689. #define CAN_F23R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  3690. #define CAN_F23R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  3691. #define CAN_F23R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  3692. #define CAN_F23R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  3693. #define CAN_F23R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  3694. #define CAN_F23R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  3695. /******************* Bit definition for CAN_F24R2 register ******************/
  3696. #define CAN_F24R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  3697. #define CAN_F24R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  3698. #define CAN_F24R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  3699. #define CAN_F24R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  3700. #define CAN_F24R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  3701. #define CAN_F24R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  3702. #define CAN_F24R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  3703. #define CAN_F24R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  3704. #define CAN_F24R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  3705. #define CAN_F24R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  3706. #define CAN_F24R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  3707. #define CAN_F24R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  3708. #define CAN_F24R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  3709. #define CAN_F24R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  3710. #define CAN_F24R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  3711. #define CAN_F24R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  3712. #define CAN_F24R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  3713. #define CAN_F24R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  3714. #define CAN_F24R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  3715. #define CAN_F24R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  3716. #define CAN_F24R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  3717. #define CAN_F24R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  3718. #define CAN_F24R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  3719. #define CAN_F24R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  3720. #define CAN_F24R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  3721. #define CAN_F24R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  3722. #define CAN_F24R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  3723. #define CAN_F24R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  3724. #define CAN_F24R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  3725. #define CAN_F24R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  3726. #define CAN_F24R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  3727. #define CAN_F24R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  3728. /******************* Bit definition for CAN_F25R2 register ******************/
  3729. #define CAN_F25R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  3730. #define CAN_F25R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  3731. #define CAN_F25R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  3732. #define CAN_F25R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  3733. #define CAN_F25R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  3734. #define CAN_F25R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  3735. #define CAN_F25R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  3736. #define CAN_F25R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  3737. #define CAN_F25R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  3738. #define CAN_F25R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  3739. #define CAN_F25R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  3740. #define CAN_F25R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  3741. #define CAN_F25R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  3742. #define CAN_F25R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  3743. #define CAN_F25R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  3744. #define CAN_F25R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  3745. #define CAN_F25R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  3746. #define CAN_F25R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  3747. #define CAN_F25R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  3748. #define CAN_F25R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  3749. #define CAN_F25R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  3750. #define CAN_F25R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  3751. #define CAN_F25R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  3752. #define CAN_F25R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  3753. #define CAN_F25R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  3754. #define CAN_F25R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  3755. #define CAN_F25R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  3756. #define CAN_F25R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  3757. #define CAN_F25R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  3758. #define CAN_F25R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  3759. #define CAN_F25R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  3760. #define CAN_F25R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  3761. /******************* Bit definition for CAN_F26R2 register ******************/
  3762. #define CAN_F26R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  3763. #define CAN_F26R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  3764. #define CAN_F26R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  3765. #define CAN_F26R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  3766. #define CAN_F26R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  3767. #define CAN_F26R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  3768. #define CAN_F26R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  3769. #define CAN_F26R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  3770. #define CAN_F26R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  3771. #define CAN_F26R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  3772. #define CAN_F26R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  3773. #define CAN_F26R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  3774. #define CAN_F26R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  3775. #define CAN_F26R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  3776. #define CAN_F26R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  3777. #define CAN_F26R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  3778. #define CAN_F26R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  3779. #define CAN_F26R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  3780. #define CAN_F26R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  3781. #define CAN_F26R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  3782. #define CAN_F26R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  3783. #define CAN_F26R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  3784. #define CAN_F26R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  3785. #define CAN_F26R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  3786. #define CAN_F26R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  3787. #define CAN_F26R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  3788. #define CAN_F26R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  3789. #define CAN_F26R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  3790. #define CAN_F26R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  3791. #define CAN_F26R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  3792. #define CAN_F26R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  3793. #define CAN_F26R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  3794. /******************* Bit definition for CAN_F27R2 register ******************/
  3795. #define CAN_F27R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */
  3796. #define CAN_F27R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */
  3797. #define CAN_F27R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */
  3798. #define CAN_F27R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */
  3799. #define CAN_F27R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */
  3800. #define CAN_F27R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */
  3801. #define CAN_F27R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */
  3802. #define CAN_F27R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */
  3803. #define CAN_F27R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */
  3804. #define CAN_F27R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */
  3805. #define CAN_F27R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */
  3806. #define CAN_F27R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */
  3807. #define CAN_F27R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */
  3808. #define CAN_F27R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */
  3809. #define CAN_F27R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */
  3810. #define CAN_F27R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */
  3811. #define CAN_F27R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */
  3812. #define CAN_F27R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */
  3813. #define CAN_F27R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */
  3814. #define CAN_F27R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */
  3815. #define CAN_F27R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */
  3816. #define CAN_F27R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */
  3817. #define CAN_F27R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */
  3818. #define CAN_F27R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */
  3819. #define CAN_F27R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */
  3820. #define CAN_F27R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */
  3821. #define CAN_F27R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */
  3822. #define CAN_F27R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */
  3823. #define CAN_F27R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */
  3824. #define CAN_F27R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */
  3825. #define CAN_F27R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */
  3826. #define CAN_F27R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */
  3827. /******************************************************************************/
  3828. /* CRC Calculation Unit */
  3829. /******************************************************************************/
  3830. /******************* Bit definition for CRC_DATAR register *********************/
  3831. #define CRC_DATAR_DR ((uint32_t)0xFFFFFFFF) /* Data register bits */
  3832. /******************* Bit definition for CRC_IDATAR register ********************/
  3833. #define CRC_IDR_IDATAR ((uint8_t)0xFF) /* General-purpose 8-bit data register bits */
  3834. /******************** Bit definition for CRC_CTLR register ********************/
  3835. #define CRC_CTLR_RESET ((uint8_t)0x01) /* RESET bit */
  3836. /******************************************************************************/
  3837. /* Digital to Analog Converter */
  3838. /******************************************************************************/
  3839. /******************** Bit definition for DAC_CTLR register ********************/
  3840. #define DAC_EN1 ((uint32_t)0x00000001) /* DAC channel1 enable */
  3841. #define DAC_BOFF1 ((uint32_t)0x00000002) /* DAC channel1 output buffer disable */
  3842. #define DAC_TEN1 ((uint32_t)0x00000004) /* DAC channel1 Trigger enable */
  3843. #define DAC_TSEL1 ((uint32_t)0x00000038) /* TSEL1[2:0] (DAC channel1 Trigger selection) */
  3844. #define DAC_TSEL1_0 ((uint32_t)0x00000008) /* Bit 0 */
  3845. #define DAC_TSEL1_1 ((uint32_t)0x00000010) /* Bit 1 */
  3846. #define DAC_TSEL1_2 ((uint32_t)0x00000020) /* Bit 2 */
  3847. #define DAC_WAVE1 ((uint32_t)0x000000C0) /* WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
  3848. #define DAC_WAVE1_0 ((uint32_t)0x00000040) /* Bit 0 */
  3849. #define DAC_WAVE1_1 ((uint32_t)0x00000080) /* Bit 1 */
  3850. #define DAC_MAMP1 ((uint32_t)0x00000F00) /* MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
  3851. #define DAC_MAMP1_0 ((uint32_t)0x00000100) /* Bit 0 */
  3852. #define DAC_MAMP1_1 ((uint32_t)0x00000200) /* Bit 1 */
  3853. #define DAC_MAMP1_2 ((uint32_t)0x00000400) /* Bit 2 */
  3854. #define DAC_MAMP1_3 ((uint32_t)0x00000800) /* Bit 3 */
  3855. #define DAC_DMAEN1 ((uint32_t)0x00001000) /* DAC channel1 DMA enable */
  3856. #define DAC_EN2 ((uint32_t)0x00010000) /* DAC channel2 enable */
  3857. #define DAC_BOFF2 ((uint32_t)0x00020000) /* DAC channel2 output buffer disable */
  3858. #define DAC_TEN2 ((uint32_t)0x00040000) /* DAC channel2 Trigger enable */
  3859. #define DAC_TSEL2 ((uint32_t)0x00380000) /* TSEL2[2:0] (DAC channel2 Trigger selection) */
  3860. #define DAC_TSEL2_0 ((uint32_t)0x00080000) /* Bit 0 */
  3861. #define DAC_TSEL2_1 ((uint32_t)0x00100000) /* Bit 1 */
  3862. #define DAC_TSEL2_2 ((uint32_t)0x00200000) /* Bit 2 */
  3863. #define DAC_WAVE2 ((uint32_t)0x00C00000) /* WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
  3864. #define DAC_WAVE2_0 ((uint32_t)0x00400000) /* Bit 0 */
  3865. #define DAC_WAVE2_1 ((uint32_t)0x00800000) /* Bit 1 */
  3866. #define DAC_MAMP2 ((uint32_t)0x0F000000) /* MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
  3867. #define DAC_MAMP2_0 ((uint32_t)0x01000000) /* Bit 0 */
  3868. #define DAC_MAMP2_1 ((uint32_t)0x02000000) /* Bit 1 */
  3869. #define DAC_MAMP2_2 ((uint32_t)0x04000000) /* Bit 2 */
  3870. #define DAC_MAMP2_3 ((uint32_t)0x08000000) /* Bit 3 */
  3871. #define DAC_DMAEN2 ((uint32_t)0x10000000) /* DAC channel2 DMA enabled */
  3872. /***************** Bit definition for DAC_SWTR register ******************/
  3873. #define DAC_SWTRIG1 ((uint8_t)0x01) /* DAC channel1 software trigger */
  3874. #define DAC_SWTRIG2 ((uint8_t)0x02) /* DAC channel2 software trigger */
  3875. /***************** Bit definition for DAC_R12BDHR1 register ******************/
  3876. #define DAC_DHR12R1 ((uint16_t)0x0FFF) /* DAC channel1 12-bit Right aligned data */
  3877. /***************** Bit definition for DAC_L12BDHR1 register ******************/
  3878. #define DAC_DHR12L1 ((uint16_t)0xFFF0) /* DAC channel1 12-bit Left aligned data */
  3879. /****************** Bit definition for DAC_R8BDHR1 register ******************/
  3880. #define DAC_DHR8R1 ((uint8_t)0xFF) /* DAC channel1 8-bit Right aligned data */
  3881. /***************** Bit definition for DAC_R12BDHR2 register ******************/
  3882. #define DAC_DHR12R2 ((uint16_t)0x0FFF) /* DAC channel2 12-bit Right aligned data */
  3883. /***************** Bit definition for DAC_L12BDHR2 register ******************/
  3884. #define DAC_DHR12L2 ((uint16_t)0xFFF0) /* DAC channel2 12-bit Left aligned data */
  3885. /****************** Bit definition for DAC_R8BDHR2 register ******************/
  3886. #define DAC_DHR8R2 ((uint8_t)0xFF) /* DAC channel2 8-bit Right aligned data */
  3887. /***************** Bit definition for DAC_RD12BDHR register ******************/
  3888. #define DAC_RD12BDHR_DACC1DHR ((uint32_t)0x00000FFF) /* DAC channel1 12-bit Right aligned data */
  3889. #define DAC_RD12BDHR_DACC2DHR ((uint32_t)0x0FFF0000) /* DAC channel2 12-bit Right aligned data */
  3890. /***************** Bit definition for DAC_LD12BDHR register ******************/
  3891. #define DAC_LD12BDHR_DACC1DHR ((uint32_t)0x0000FFF0) /* DAC channel1 12-bit Left aligned data */
  3892. #define DAC_LD12BDHR_DACC2DHR ((uint32_t)0xFFF00000) /* DAC channel2 12-bit Left aligned data */
  3893. /****************** Bit definition for DAC_RD8BDHR register ******************/
  3894. #define DAC_RD8BDHR_DACC1DHR ((uint16_t)0x00FF) /* DAC channel1 8-bit Right aligned data */
  3895. #define DAC_RD8BDHR_DACC2DHR ((uint16_t)0xFF00) /* DAC channel2 8-bit Right aligned data */
  3896. /******************* Bit definition for DAC_DOR1 register *******************/
  3897. #define DAC_DACC1DOR ((uint16_t)0x0FFF) /* DAC channel1 data output */
  3898. /******************* Bit definition for DAC_DOR2 register *******************/
  3899. #define DAC_DACC2DOR ((uint16_t)0x0FFF) /* DAC channel2 data output */
  3900. /******************************************************************************/
  3901. /* DMA Controller */
  3902. /******************************************************************************/
  3903. /******************* Bit definition for DMA_INTFR register ********************/
  3904. #define DMA_GIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt flag */
  3905. #define DMA_TCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete flag */
  3906. #define DMA_HTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer flag */
  3907. #define DMA_TEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error flag */
  3908. #define DMA_GIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt flag */
  3909. #define DMA_TCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete flag */
  3910. #define DMA_HTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer flag */
  3911. #define DMA_TEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error flag */
  3912. #define DMA_GIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt flag */
  3913. #define DMA_TCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete flag */
  3914. #define DMA_HTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer flag */
  3915. #define DMA_TEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error flag */
  3916. #define DMA_GIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt flag */
  3917. #define DMA_TCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete flag */
  3918. #define DMA_HTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer flag */
  3919. #define DMA_TEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error flag */
  3920. #define DMA_GIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt flag */
  3921. #define DMA_TCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete flag */
  3922. #define DMA_HTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer flag */
  3923. #define DMA_TEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error flag */
  3924. #define DMA_GIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt flag */
  3925. #define DMA_TCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete flag */
  3926. #define DMA_HTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer flag */
  3927. #define DMA_TEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error flag */
  3928. #define DMA_GIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt flag */
  3929. #define DMA_TCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete flag */
  3930. #define DMA_HTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */
  3931. #define DMA_TEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */
  3932. #define DMA_GIF8 ((uint32_t)0x00000001) /* Channel 8 Global interrupt flag */
  3933. #define DMA_TCIF8 ((uint32_t)0x00000002) /* Channel 8 Transfer Complete flag */
  3934. #define DMA_HTIF8 ((uint32_t)0x00000004) /* Channel 8 Half Transfer flag */
  3935. #define DMA_TEIF8 ((uint32_t)0x00000008) /* Channel 8 Transfer Error flag */
  3936. #define DMA_GIF9 ((uint32_t)0x00000010) /* Channel 9 Global interrupt flag */
  3937. #define DMA_TCIF9 ((uint32_t)0x00000020) /* Channel 9 Transfer Complete flag */
  3938. #define DMA_HTIF9 ((uint32_t)0x00000040) /* Channel 9 Half Transfer flag */
  3939. #define DMA_TEIF9 ((uint32_t)0x00000080) /* Channel 9 Transfer Error flag */
  3940. #define DMA_GIF10 ((uint32_t)0x00000100) /* Channel 10 Global interrupt flag */
  3941. #define DMA_TCIF10 ((uint32_t)0x00000200) /* Channel 10 Transfer Complete flag */
  3942. #define DMA_HTIF10 ((uint32_t)0x00000400) /* Channel 10 Half Transfer flag */
  3943. #define DMA_TEIF10 ((uint32_t)0x00000800) /* Channel 10 Transfer Error flag */
  3944. #define DMA_GIF11 ((uint32_t)0x00001000) /* Channel 11 Global interrupt flag */
  3945. #define DMA_TCIF11 ((uint32_t)0x00002000) /* Channel 11 Transfer Complete flag */
  3946. #define DMA_HTIF11 ((uint32_t)0x00004000) /* Channel 11 Half Transfer flag */
  3947. #define DMA_TEIF11 ((uint32_t)0x00008000) /* Channel 11 Transfer Error flag */
  3948. /******************* Bit definition for DMA_INTFCR register *******************/
  3949. #define DMA_CGIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt clear */
  3950. #define DMA_CTCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */
  3951. #define DMA_CHTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer clear */
  3952. #define DMA_CTEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error clear */
  3953. #define DMA_CGIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt clear */
  3954. #define DMA_CTCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete clear */
  3955. #define DMA_CHTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer clear */
  3956. #define DMA_CTEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error clear */
  3957. #define DMA_CGIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt clear */
  3958. #define DMA_CTCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete clear */
  3959. #define DMA_CHTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer clear */
  3960. #define DMA_CTEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error clear */
  3961. #define DMA_CGIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt clear */
  3962. #define DMA_CTCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete clear */
  3963. #define DMA_CHTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer clear */
  3964. #define DMA_CTEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error clear */
  3965. #define DMA_CGIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt clear */
  3966. #define DMA_CTCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete clear */
  3967. #define DMA_CHTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer clear */
  3968. #define DMA_CTEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error clear */
  3969. #define DMA_CGIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt clear */
  3970. #define DMA_CTCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete clear */
  3971. #define DMA_CHTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer clear */
  3972. #define DMA_CTEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error clear */
  3973. #define DMA_CGIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt clear */
  3974. #define DMA_CTCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete clear */
  3975. #define DMA_CHTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer clear */
  3976. #define DMA_CTEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error clear */
  3977. #define DMA_CGIF8 ((uint32_t)0x10000000) /* Channel 8 Global interrupt clear */
  3978. #define DMA_CTCIF8 ((uint32_t)0x20000000) /* Channel 8 Transfer Complete clear */
  3979. #define DMA_CHTIF8 ((uint32_t)0x40000000) /* Channel 8 Half Transfer clear */
  3980. #define DMA_CTEIF8 ((uint32_t)0x80000000) /* Channel 8 Transfer Error clear */
  3981. /******************* Bit definition for DMA_CFGR1 register *******************/
  3982. #define DMA_CFGR1_EN ((uint16_t)0x0001) /* Channel enable*/
  3983. #define DMA_CFGR1_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */
  3984. #define DMA_CFGR1_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */
  3985. #define DMA_CFGR1_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */
  3986. #define DMA_CFGR1_DIR ((uint16_t)0x0010) /* Data transfer direction */
  3987. #define DMA_CFGR1_CIRC ((uint16_t)0x0020) /* Circular mode */
  3988. #define DMA_CFGR1_PINC ((uint16_t)0x0040) /* Peripheral increment mode */
  3989. #define DMA_CFGR1_MINC ((uint16_t)0x0080) /* Memory increment mode */
  3990. #define DMA_CFGR1_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
  3991. #define DMA_CFGR1_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */
  3992. #define DMA_CFGR1_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */
  3993. #define DMA_CFGR1_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */
  3994. #define DMA_CFGR1_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */
  3995. #define DMA_CFGR1_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */
  3996. #define DMA_CFGR1_PL ((uint16_t)0x3000) /* PL[1:0] bits(Channel Priority level) */
  3997. #define DMA_CFGR1_PL_0 ((uint16_t)0x1000) /* Bit 0 */
  3998. #define DMA_CFGR1_PL_1 ((uint16_t)0x2000) /* Bit 1 */
  3999. #define DMA_CFGR1_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */
  4000. /******************* Bit definition for DMA_CFGR2 register *******************/
  4001. #define DMA_CFGR2_EN ((uint16_t)0x0001) /* Channel enable */
  4002. #define DMA_CFGR2_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */
  4003. #define DMA_CFGR2_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */
  4004. #define DMA_CFGR2_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */
  4005. #define DMA_CFGR2_DIR ((uint16_t)0x0010) /* Data transfer direction */
  4006. #define DMA_CFGR2_CIRC ((uint16_t)0x0020) /* Circular mode */
  4007. #define DMA_CFGR2_PINC ((uint16_t)0x0040) /* Peripheral increment mode */
  4008. #define DMA_CFGR2_MINC ((uint16_t)0x0080) /* Memory increment mode */
  4009. #define DMA_CFGR2_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
  4010. #define DMA_CFGR2_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */
  4011. #define DMA_CFGR2_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */
  4012. #define DMA_CFGR2_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */
  4013. #define DMA_CFGR2_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */
  4014. #define DMA_CFGR2_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */
  4015. #define DMA_CFGR2_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */
  4016. #define DMA_CFGR2_PL_0 ((uint16_t)0x1000) /* Bit 0 */
  4017. #define DMA_CFGR2_PL_1 ((uint16_t)0x2000) /* Bit 1 */
  4018. #define DMA_CFGR2_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */
  4019. /******************* Bit definition for DMA_CFGR3 register *******************/
  4020. #define DMA_CFGR3_EN ((uint16_t)0x0001) /* Channel enable */
  4021. #define DMA_CFGR3_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */
  4022. #define DMA_CFGR3_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */
  4023. #define DMA_CFGR3_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */
  4024. #define DMA_CFGR3_DIR ((uint16_t)0x0010) /* Data transfer direction */
  4025. #define DMA_CFGR3_CIRC ((uint16_t)0x0020) /* Circular mode */
  4026. #define DMA_CFGR3_PINC ((uint16_t)0x0040) /* Peripheral increment mode */
  4027. #define DMA_CFGR3_MINC ((uint16_t)0x0080) /* Memory increment mode */
  4028. #define DMA_CFGR3_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
  4029. #define DMA_CFGR3_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */
  4030. #define DMA_CFGR3_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */
  4031. #define DMA_CFGR3_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */
  4032. #define DMA_CFGR3_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */
  4033. #define DMA_CFGR3_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */
  4034. #define DMA_CFGR3_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */
  4035. #define DMA_CFGR3_PL_0 ((uint16_t)0x1000) /* Bit 0 */
  4036. #define DMA_CFGR3_PL_1 ((uint16_t)0x2000) /* Bit 1 */
  4037. #define DMA_CFGR3_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */
  4038. /******************* Bit definition for DMA_CFG4 register *******************/
  4039. #define DMA_CFG4_EN ((uint16_t)0x0001) /* Channel enable */
  4040. #define DMA_CFG4_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */
  4041. #define DMA_CFG4_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */
  4042. #define DMA_CFG4_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */
  4043. #define DMA_CFG4_DIR ((uint16_t)0x0010) /* Data transfer direction */
  4044. #define DMA_CFG4_CIRC ((uint16_t)0x0020) /* Circular mode */
  4045. #define DMA_CFG4_PINC ((uint16_t)0x0040) /* Peripheral increment mode */
  4046. #define DMA_CFG4_MINC ((uint16_t)0x0080) /* Memory increment mode */
  4047. #define DMA_CFG4_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
  4048. #define DMA_CFG4_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */
  4049. #define DMA_CFG4_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */
  4050. #define DMA_CFG4_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */
  4051. #define DMA_CFG4_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */
  4052. #define DMA_CFG4_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */
  4053. #define DMA_CFG4_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */
  4054. #define DMA_CFG4_PL_0 ((uint16_t)0x1000) /* Bit 0 */
  4055. #define DMA_CFG4_PL_1 ((uint16_t)0x2000) /* Bit 1 */
  4056. #define DMA_CFG4_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */
  4057. /****************** Bit definition for DMA_CFG5 register *******************/
  4058. #define DMA_CFG5_EN ((uint16_t)0x0001) /* Channel enable */
  4059. #define DMA_CFG5_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */
  4060. #define DMA_CFG5_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */
  4061. #define DMA_CFG5_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */
  4062. #define DMA_CFG5_DIR ((uint16_t)0x0010) /* Data transfer direction */
  4063. #define DMA_CFG5_CIRC ((uint16_t)0x0020) /* Circular mode */
  4064. #define DMA_CFG5_PINC ((uint16_t)0x0040) /* Peripheral increment mode */
  4065. #define DMA_CFG5_MINC ((uint16_t)0x0080) /* Memory increment mode */
  4066. #define DMA_CFG5_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
  4067. #define DMA_CFG5_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */
  4068. #define DMA_CFG5_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */
  4069. #define DMA_CFG5_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */
  4070. #define DMA_CFG5_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */
  4071. #define DMA_CFG5_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */
  4072. #define DMA_CFG5_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */
  4073. #define DMA_CFG5_PL_0 ((uint16_t)0x1000) /* Bit 0 */
  4074. #define DMA_CFG5_PL_1 ((uint16_t)0x2000) /* Bit 1 */
  4075. #define DMA_CFG5_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */
  4076. /******************* Bit definition for DMA_CFG6 register *******************/
  4077. #define DMA_CFG6_EN ((uint16_t)0x0001) /* Channel enable */
  4078. #define DMA_CFG6_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */
  4079. #define DMA_CFG6_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */
  4080. #define DMA_CFG6_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */
  4081. #define DMA_CFG6_DIR ((uint16_t)0x0010) /* Data transfer direction */
  4082. #define DMA_CFG6_CIRC ((uint16_t)0x0020) /* Circular mode */
  4083. #define DMA_CFG6_PINC ((uint16_t)0x0040) /* Peripheral increment mode */
  4084. #define DMA_CFG6_MINC ((uint16_t)0x0080) /* Memory increment mode */
  4085. #define DMA_CFG6_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
  4086. #define DMA_CFG6_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */
  4087. #define DMA_CFG6_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */
  4088. #define DMA_CFG6_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */
  4089. #define DMA_CFG6_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */
  4090. #define DMA_CFG6_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */
  4091. #define DMA_CFG6_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */
  4092. #define DMA_CFG6_PL_0 ((uint16_t)0x1000) /* Bit 0 */
  4093. #define DMA_CFG6_PL_1 ((uint16_t)0x2000) /* Bit 1 */
  4094. #define DMA_CFG6_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */
  4095. /******************* Bit definition for DMA_CFG7 register *******************/
  4096. #define DMA_CFG7_EN ((uint16_t)0x0001) /* Channel enable */
  4097. #define DMA_CFG7_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */
  4098. #define DMA_CFG7_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */
  4099. #define DMA_CFG7_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */
  4100. #define DMA_CFG7_DIR ((uint16_t)0x0010) /* Data transfer direction */
  4101. #define DMA_CFG7_CIRC ((uint16_t)0x0020) /* Circular mode */
  4102. #define DMA_CFG7_PINC ((uint16_t)0x0040) /* Peripheral increment mode */
  4103. #define DMA_CFG7_MINC ((uint16_t)0x0080) /* Memory increment mode */
  4104. #define DMA_CFG7_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
  4105. #define DMA_CFG7_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */
  4106. #define DMA_CFG7_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */
  4107. #define DMA_CFG7_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */
  4108. #define DMA_CFG7_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */
  4109. #define DMA_CFG7_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */
  4110. #define DMA_CFG7_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */
  4111. #define DMA_CFG7_PL_0 ((uint16_t)0x1000) /* Bit 0 */
  4112. #define DMA_CFG7_PL_1 ((uint16_t)0x2000) /* Bit 1 */
  4113. #define DMA_CFG7_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */
  4114. /****************** Bit definition for DMA_CNTR1 register ******************/
  4115. #define DMA_CNTR1_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */
  4116. /****************** Bit definition for DMA_CNTR2 register ******************/
  4117. #define DMA_CNTR2_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */
  4118. /****************** Bit definition for DMA_CNTR3 register ******************/
  4119. #define DMA_CNTR3_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */
  4120. /****************** Bit definition for DMA_CNTR4 register ******************/
  4121. #define DMA_CNTR4_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */
  4122. /****************** Bit definition for DMA_CNTR5 register ******************/
  4123. #define DMA_CNTR5_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */
  4124. /****************** Bit definition for DMA_CNTR6 register ******************/
  4125. #define DMA_CNTR6_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */
  4126. /****************** Bit definition for DMA_CNTR7 register ******************/
  4127. #define DMA_CNTR7_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */
  4128. /****************** Bit definition for DMA_CNTR8 register ******************/
  4129. #define DMA_CNTR8_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */
  4130. /****************** Bit definition for DMA_PADDR1 register *******************/
  4131. #define DMA_PADDR1_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */
  4132. /****************** Bit definition for DMA_PADDR2 register *******************/
  4133. #define DMA_PADDR2_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */
  4134. /****************** Bit definition for DMA_PADDR3 register *******************/
  4135. #define DMA_PADDR3_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */
  4136. /****************** Bit definition for DMA_PADDR4 register *******************/
  4137. #define DMA_PADDR4_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */
  4138. /****************** Bit definition for DMA_PADDR5 register *******************/
  4139. #define DMA_PADDR5_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */
  4140. /****************** Bit definition for DMA_PADDR6 register *******************/
  4141. #define DMA_PADDR6_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */
  4142. /****************** Bit definition for DMA_PADDR7 register *******************/
  4143. #define DMA_PADDR7_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */
  4144. /****************** Bit definition for DMA_PADDR8 register *******************/
  4145. #define DMA_PADDR8_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */
  4146. /****************** Bit definition for DMA_MADDR1 register *******************/
  4147. #define DMA_MADDR1_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */
  4148. /****************** Bit definition for DMA_MADDR2 register *******************/
  4149. #define DMA_MADDR2_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */
  4150. /****************** Bit definition for DMA_MADDR3 register *******************/
  4151. #define DMA_MADDR3_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */
  4152. /****************** Bit definition for DMA_MADDR4 register *******************/
  4153. #define DMA_MADDR4_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */
  4154. /****************** Bit definition for DMA_MADDR5 register *******************/
  4155. #define DMA_MADDR5_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */
  4156. /****************** Bit definition for DMA_MADDR6 register *******************/
  4157. #define DMA_MADDR6_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */
  4158. /****************** Bit definition for DMA_MADDR7 register *******************/
  4159. #define DMA_MADDR7_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */
  4160. /****************** Bit definition for DMA_MADDR8 register *******************/
  4161. #define DMA_MADDR8_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */
  4162. /******************************************************************************/
  4163. /* External Interrupt/Event Controller */
  4164. /******************************************************************************/
  4165. /******************* Bit definition for EXTI_INTENR register *******************/
  4166. #define EXTI_INTENR_MR0 ((uint32_t)0x00000001) /* Interrupt Mask on line 0 */
  4167. #define EXTI_INTENR_MR1 ((uint32_t)0x00000002) /* Interrupt Mask on line 1 */
  4168. #define EXTI_INTENR_MR2 ((uint32_t)0x00000004) /* Interrupt Mask on line 2 */
  4169. #define EXTI_INTENR_MR3 ((uint32_t)0x00000008) /* Interrupt Mask on line 3 */
  4170. #define EXTI_INTENR_MR4 ((uint32_t)0x00000010) /* Interrupt Mask on line 4 */
  4171. #define EXTI_INTENR_MR5 ((uint32_t)0x00000020) /* Interrupt Mask on line 5 */
  4172. #define EXTI_INTENR_MR6 ((uint32_t)0x00000040) /* Interrupt Mask on line 6 */
  4173. #define EXTI_INTENR_MR7 ((uint32_t)0x00000080) /* Interrupt Mask on line 7 */
  4174. #define EXTI_INTENR_MR8 ((uint32_t)0x00000100) /* Interrupt Mask on line 8 */
  4175. #define EXTI_INTENR_MR9 ((uint32_t)0x00000200) /* Interrupt Mask on line 9 */
  4176. #define EXTI_INTENR_MR10 ((uint32_t)0x00000400) /* Interrupt Mask on line 10 */
  4177. #define EXTI_INTENR_MR11 ((uint32_t)0x00000800) /* Interrupt Mask on line 11 */
  4178. #define EXTI_INTENR_MR12 ((uint32_t)0x00001000) /* Interrupt Mask on line 12 */
  4179. #define EXTI_INTENR_MR13 ((uint32_t)0x00002000) /* Interrupt Mask on line 13 */
  4180. #define EXTI_INTENR_MR14 ((uint32_t)0x00004000) /* Interrupt Mask on line 14 */
  4181. #define EXTI_INTENR_MR15 ((uint32_t)0x00008000) /* Interrupt Mask on line 15 */
  4182. #define EXTI_INTENR_MR16 ((uint32_t)0x00010000) /* Interrupt Mask on line 16 */
  4183. #define EXTI_INTENR_MR17 ((uint32_t)0x00020000) /* Interrupt Mask on line 17 */
  4184. #define EXTI_INTENR_MR18 ((uint32_t)0x00040000) /* Interrupt Mask on line 18 */
  4185. #define EXTI_INTENR_MR19 ((uint32_t)0x00080000) /* Interrupt Mask on line 19 */
  4186. #define EXTI_INTENR_MR20 ((uint32_t)0x00100000) /* Interrupt Mask on line 20 */
  4187. /******************* Bit definition for EXTI_EVENR register *******************/
  4188. #define EXTI_EVENR_MR0 ((uint32_t)0x00000001) /* Event Mask on line 0 */
  4189. #define EXTI_EVENR_MR1 ((uint32_t)0x00000002) /* Event Mask on line 1 */
  4190. #define EXTI_EVENR_MR2 ((uint32_t)0x00000004) /* Event Mask on line 2 */
  4191. #define EXTI_EVENR_MR3 ((uint32_t)0x00000008) /* Event Mask on line 3 */
  4192. #define EXTI_EVENR_MR4 ((uint32_t)0x00000010) /* Event Mask on line 4 */
  4193. #define EXTI_EVENR_MR5 ((uint32_t)0x00000020) /* Event Mask on line 5 */
  4194. #define EXTI_EVENR_MR6 ((uint32_t)0x00000040) /* Event Mask on line 6 */
  4195. #define EXTI_EVENR_MR7 ((uint32_t)0x00000080) /* Event Mask on line 7 */
  4196. #define EXTI_EVENR_MR8 ((uint32_t)0x00000100) /* Event Mask on line 8 */
  4197. #define EXTI_EVENR_MR9 ((uint32_t)0x00000200) /* Event Mask on line 9 */
  4198. #define EXTI_EVENR_MR10 ((uint32_t)0x00000400) /* Event Mask on line 10 */
  4199. #define EXTI_EVENR_MR11 ((uint32_t)0x00000800) /* Event Mask on line 11 */
  4200. #define EXTI_EVENR_MR12 ((uint32_t)0x00001000) /* Event Mask on line 12 */
  4201. #define EXTI_EVENR_MR13 ((uint32_t)0x00002000) /* Event Mask on line 13 */
  4202. #define EXTI_EVENR_MR14 ((uint32_t)0x00004000) /* Event Mask on line 14 */
  4203. #define EXTI_EVENR_MR15 ((uint32_t)0x00008000) /* Event Mask on line 15 */
  4204. #define EXTI_EVENR_MR16 ((uint32_t)0x00010000) /* Event Mask on line 16 */
  4205. #define EXTI_EVENR_MR17 ((uint32_t)0x00020000) /* Event Mask on line 17 */
  4206. #define EXTI_EVENR_MR18 ((uint32_t)0x00040000) /* Event Mask on line 18 */
  4207. #define EXTI_EVENR_MR19 ((uint32_t)0x00080000) /* Event Mask on line 19 */
  4208. #define EXTI_EVENR_MR20 ((uint32_t)0x00100000) /* Event Mask on line 20 */
  4209. /****************** Bit definition for EXTI_RTENR register *******************/
  4210. #define EXTI_RTENR_TR0 ((uint32_t)0x00000001) /* Rising trigger event configuration bit of line 0 */
  4211. #define EXTI_RTENR_TR1 ((uint32_t)0x00000002) /* Rising trigger event configuration bit of line 1 */
  4212. #define EXTI_RTENR_TR2 ((uint32_t)0x00000004) /* Rising trigger event configuration bit of line 2 */
  4213. #define EXTI_RTENR_TR3 ((uint32_t)0x00000008) /* Rising trigger event configuration bit of line 3 */
  4214. #define EXTI_RTENR_TR4 ((uint32_t)0x00000010) /* Rising trigger event configuration bit of line 4 */
  4215. #define EXTI_RTENR_TR5 ((uint32_t)0x00000020) /* Rising trigger event configuration bit of line 5 */
  4216. #define EXTI_RTENR_TR6 ((uint32_t)0x00000040) /* Rising trigger event configuration bit of line 6 */
  4217. #define EXTI_RTENR_TR7 ((uint32_t)0x00000080) /* Rising trigger event configuration bit of line 7 */
  4218. #define EXTI_RTENR_TR8 ((uint32_t)0x00000100) /* Rising trigger event configuration bit of line 8 */
  4219. #define EXTI_RTENR_TR9 ((uint32_t)0x00000200) /* Rising trigger event configuration bit of line 9 */
  4220. #define EXTI_RTENR_TR10 ((uint32_t)0x00000400) /* Rising trigger event configuration bit of line 10 */
  4221. #define EXTI_RTENR_TR11 ((uint32_t)0x00000800) /* Rising trigger event configuration bit of line 11 */
  4222. #define EXTI_RTENR_TR12 ((uint32_t)0x00001000) /* Rising trigger event configuration bit of line 12 */
  4223. #define EXTI_RTENR_TR13 ((uint32_t)0x00002000) /* Rising trigger event configuration bit of line 13 */
  4224. #define EXTI_RTENR_TR14 ((uint32_t)0x00004000) /* Rising trigger event configuration bit of line 14 */
  4225. #define EXTI_RTENR_TR15 ((uint32_t)0x00008000) /* Rising trigger event configuration bit of line 15 */
  4226. #define EXTI_RTENR_TR16 ((uint32_t)0x00010000) /* Rising trigger event configuration bit of line 16 */
  4227. #define EXTI_RTENR_TR17 ((uint32_t)0x00020000) /* Rising trigger event configuration bit of line 17 */
  4228. #define EXTI_RTENR_TR18 ((uint32_t)0x00040000) /* Rising trigger event configuration bit of line 18 */
  4229. #define EXTI_RTENR_TR19 ((uint32_t)0x00080000) /* Rising trigger event configuration bit of line 19 */
  4230. #define EXTI_RTENR_TR20 ((uint32_t)0x00100000) /* Rising trigger event configuration bit of line 20 */
  4231. /****************** Bit definition for EXTI_FTENR register *******************/
  4232. #define EXTI_FTENR_TR0 ((uint32_t)0x00000001) /* Falling trigger event configuration bit of line 0 */
  4233. #define EXTI_FTENR_TR1 ((uint32_t)0x00000002) /* Falling trigger event configuration bit of line 1 */
  4234. #define EXTI_FTENR_TR2 ((uint32_t)0x00000004) /* Falling trigger event configuration bit of line 2 */
  4235. #define EXTI_FTENR_TR3 ((uint32_t)0x00000008) /* Falling trigger event configuration bit of line 3 */
  4236. #define EXTI_FTENR_TR4 ((uint32_t)0x00000010) /* Falling trigger event configuration bit of line 4 */
  4237. #define EXTI_FTENR_TR5 ((uint32_t)0x00000020) /* Falling trigger event configuration bit of line 5 */
  4238. #define EXTI_FTENR_TR6 ((uint32_t)0x00000040) /* Falling trigger event configuration bit of line 6 */
  4239. #define EXTI_FTENR_TR7 ((uint32_t)0x00000080) /* Falling trigger event configuration bit of line 7 */
  4240. #define EXTI_FTENR_TR8 ((uint32_t)0x00000100) /* Falling trigger event configuration bit of line 8 */
  4241. #define EXTI_FTENR_TR9 ((uint32_t)0x00000200) /* Falling trigger event configuration bit of line 9 */
  4242. #define EXTI_FTENR_TR10 ((uint32_t)0x00000400) /* Falling trigger event configuration bit of line 10 */
  4243. #define EXTI_FTENR_TR11 ((uint32_t)0x00000800) /* Falling trigger event configuration bit of line 11 */
  4244. #define EXTI_FTENR_TR12 ((uint32_t)0x00001000) /* Falling trigger event configuration bit of line 12 */
  4245. #define EXTI_FTENR_TR13 ((uint32_t)0x00002000) /* Falling trigger event configuration bit of line 13 */
  4246. #define EXTI_FTENR_TR14 ((uint32_t)0x00004000) /* Falling trigger event configuration bit of line 14 */
  4247. #define EXTI_FTENR_TR15 ((uint32_t)0x00008000) /* Falling trigger event configuration bit of line 15 */
  4248. #define EXTI_FTENR_TR16 ((uint32_t)0x00010000) /* Falling trigger event configuration bit of line 16 */
  4249. #define EXTI_FTENR_TR17 ((uint32_t)0x00020000) /* Falling trigger event configuration bit of line 17 */
  4250. #define EXTI_FTENR_TR18 ((uint32_t)0x00040000) /* Falling trigger event configuration bit of line 18 */
  4251. #define EXTI_FTENR_TR19 ((uint32_t)0x00080000) /* Falling trigger event configuration bit of line 19 */
  4252. #define EXTI_FTENR_TR20 ((uint32_t)0x00100000) /* Falling trigger event configuration bit of line 20 */
  4253. /****************** Bit definition for EXTI_SWIEVR register ******************/
  4254. #define EXTI_SWIEVR_SWIEVR0 ((uint32_t)0x00000001) /* Software Interrupt on line 0 */
  4255. #define EXTI_SWIEVR_SWIEVR1 ((uint32_t)0x00000002) /* Software Interrupt on line 1 */
  4256. #define EXTI_SWIEVR_SWIEVR2 ((uint32_t)0x00000004) /* Software Interrupt on line 2 */
  4257. #define EXTI_SWIEVR_SWIEVR3 ((uint32_t)0x00000008) /* Software Interrupt on line 3 */
  4258. #define EXTI_SWIEVR_SWIEVR4 ((uint32_t)0x00000010) /* Software Interrupt on line 4 */
  4259. #define EXTI_SWIEVR_SWIEVR5 ((uint32_t)0x00000020) /* Software Interrupt on line 5 */
  4260. #define EXTI_SWIEVR_SWIEVR6 ((uint32_t)0x00000040) /* Software Interrupt on line 6 */
  4261. #define EXTI_SWIEVR_SWIEVR7 ((uint32_t)0x00000080) /* Software Interrupt on line 7 */
  4262. #define EXTI_SWIEVR_SWIEVR8 ((uint32_t)0x00000100) /* Software Interrupt on line 8 */
  4263. #define EXTI_SWIEVR_SWIEVR9 ((uint32_t)0x00000200) /* Software Interrupt on line 9 */
  4264. #define EXTI_SWIEVR_SWIEVR10 ((uint32_t)0x00000400) /* Software Interrupt on line 10 */
  4265. #define EXTI_SWIEVR_SWIEVR11 ((uint32_t)0x00000800) /* Software Interrupt on line 11 */
  4266. #define EXTI_SWIEVR_SWIEVR12 ((uint32_t)0x00001000) /* Software Interrupt on line 12 */
  4267. #define EXTI_SWIEVR_SWIEVR13 ((uint32_t)0x00002000) /* Software Interrupt on line 13 */
  4268. #define EXTI_SWIEVR_SWIEVR14 ((uint32_t)0x00004000) /* Software Interrupt on line 14 */
  4269. #define EXTI_SWIEVR_SWIEVR15 ((uint32_t)0x00008000) /* Software Interrupt on line 15 */
  4270. #define EXTI_SWIEVR_SWIEVR16 ((uint32_t)0x00010000) /* Software Interrupt on line 16 */
  4271. #define EXTI_SWIEVR_SWIEVR17 ((uint32_t)0x00020000) /* Software Interrupt on line 17 */
  4272. #define EXTI_SWIEVR_SWIEVR18 ((uint32_t)0x00040000) /* Software Interrupt on line 18 */
  4273. #define EXTI_SWIEVR_SWIEVR19 ((uint32_t)0x00080000) /* Software Interrupt on line 19 */
  4274. #define EXTI_SWIEVR_SWIEVR20 ((uint32_t)0x00100000) /* Software Interrupt on line 20 */
  4275. /******************* Bit definition for EXTI_INTFR register ********************/
  4276. #define EXTI_INTF_INTF0 ((uint32_t)0x00000001) /* Pending bit for line 0 */
  4277. #define EXTI_INTF_INTF1 ((uint32_t)0x00000002) /* Pending bit for line 1 */
  4278. #define EXTI_INTF_INTF2 ((uint32_t)0x00000004) /* Pending bit for line 2 */
  4279. #define EXTI_INTF_INTF3 ((uint32_t)0x00000008) /* Pending bit for line 3 */
  4280. #define EXTI_INTF_INTF4 ((uint32_t)0x00000010) /* Pending bit for line 4 */
  4281. #define EXTI_INTF_INTF5 ((uint32_t)0x00000020) /* Pending bit for line 5 */
  4282. #define EXTI_INTF_INTF6 ((uint32_t)0x00000040) /* Pending bit for line 6 */
  4283. #define EXTI_INTF_INTF7 ((uint32_t)0x00000080) /* Pending bit for line 7 */
  4284. #define EXTI_INTF_INTF8 ((uint32_t)0x00000100) /* Pending bit for line 8 */
  4285. #define EXTI_INTF_INTF9 ((uint32_t)0x00000200) /* Pending bit for line 9 */
  4286. #define EXTI_INTF_INTF10 ((uint32_t)0x00000400) /* Pending bit for line 10 */
  4287. #define EXTI_INTF_INTF11 ((uint32_t)0x00000800) /* Pending bit for line 11 */
  4288. #define EXTI_INTF_INTF12 ((uint32_t)0x00001000) /* Pending bit for line 12 */
  4289. #define EXTI_INTF_INTF13 ((uint32_t)0x00002000) /* Pending bit for line 13 */
  4290. #define EXTI_INTF_INTF14 ((uint32_t)0x00004000) /* Pending bit for line 14 */
  4291. #define EXTI_INTF_INTF15 ((uint32_t)0x00008000) /* Pending bit for line 15 */
  4292. #define EXTI_INTF_INTF16 ((uint32_t)0x00010000) /* Pending bit for line 16 */
  4293. #define EXTI_INTF_INTF17 ((uint32_t)0x00020000) /* Pending bit for line 17 */
  4294. #define EXTI_INTF_INTF18 ((uint32_t)0x00040000) /* Pending bit for line 18 */
  4295. #define EXTI_INTF_INTF19 ((uint32_t)0x00080000) /* Pending bit for line 19 */
  4296. #define EXTI_INTF_INTF20 ((uint32_t)0x00100000) /* Pending bit for line 20 */
  4297. /******************************************************************************/
  4298. /* FLASH and Option Bytes Registers */
  4299. /******************************************************************************/
  4300. /******************* Bit definition for FLASH_ACTLR register ******************/
  4301. /****************** Bit definition for FLASH_KEYR register ******************/
  4302. #define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /* FPEC Key */
  4303. #define FLASH_KEYR_KEY1 ((uint32_t)0x45670123)
  4304. #define FLASH_KEYR_KEY2 ((uint32_t)0xCDEF89AB)
  4305. /***************** Bit definition for FLASH_OBKEYR register ****************/
  4306. #define FLASH_OBKEYR_OBKEYR ((uint32_t)0xFFFFFFFF) /* Option Byte Key */
  4307. /****************** Bit definition for FLASH_STATR register *******************/
  4308. #define FLASH_STATR_BSY ((uint8_t)0x01) /* Busy */
  4309. #define FLASH_STATR_WRBSY ((uint8_t)0x02)
  4310. #define FLASH_STATR_WRPRTERR ((uint8_t)0x10) /* Write Protection Error */
  4311. #define FLASH_STATR_EOP ((uint8_t)0x20) /* End of operation */
  4312. #define FLASH_STATR_EHMODS ((uint8_t)0x80)
  4313. /******************* Bit definition for FLASH_CTLR register *******************/
  4314. #define FLASH_CTLR_PG ((uint32_t)0x00000001) /* Programming */
  4315. #define FLASH_CTLR_PER ((uint32_t)0x00000002) /* Sector Erase 4K */
  4316. #define FLASH_CTLR_MER ((uint32_t)0x00000004) /* Mass Erase */
  4317. #define FLASH_CTLR_OPTPG ((uint32_t)0x00000010) /* Option Byte Programming */
  4318. #define FLASH_CTLR_OPTER ((uint32_t)0x00000020) /* Option Byte Erase */
  4319. #define FLASH_CTLR_STRT ((uint32_t)0x00000040) /* Start */
  4320. #define FLASH_CTLR_LOCK ((uint32_t)0x00000080) /* Lock */
  4321. #define FLASH_CTLR_OPTWRE ((uint32_t)0x00000200) /* Option Bytes Write Enable */
  4322. #define FLASH_CTLR_ERRIE ((uint32_t)0x00000400) /* Error Interrupt Enable */
  4323. #define FLASH_CTLR_EOPIE ((uint32_t)0x00001000) /* End of operation interrupt enable */
  4324. #define FLASH_CTLR_FAST_LOCK ((uint32_t)0x00008000) /* Fast Lock */
  4325. #define FLASH_CTLR_PAGE_PG ((uint32_t)0x00010000) /* Page Programming 256Byte */
  4326. #define FLASH_CTLR_PAGE_ER ((uint32_t)0x00020000) /* Page Erase 256Byte */
  4327. #define FLASH_CTLR_PAGE_BER32 ((uint32_t)0x00040000) /* Block Erase 32K */
  4328. #define FLASH_CTLR_PAGE_BER64 ((uint32_t)0x00080000) /* Block Erase 64K */
  4329. #define FLASH_CTLR_PG_STRT ((uint32_t)0x00200000) /* Page Programming Start */
  4330. #define FLASH_CTLR_RSENACT ((uint32_t)0x00400000)
  4331. #define FLASH_CTLR_EHMOD ((uint32_t)0x01000000)
  4332. #define FLASH_CTLR_SCKMOD ((uint32_t)0x02000000)
  4333. /******************* Bit definition for FLASH_ADDR register *******************/
  4334. #define FLASH_ADDR_FAR ((uint32_t)0xFFFFFFFF) /* Flash Address */
  4335. /****************** Bit definition for FLASH_OBR register *******************/
  4336. #define FLASH_OBR_OPTERR ((uint16_t)0x0001) /* Option Byte Error */
  4337. #define FLASH_OBR_RDPRT ((uint16_t)0x0002) /* Read protection */
  4338. #define FLASH_OBR_USER ((uint16_t)0x03FC) /* User Option Bytes */
  4339. #define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /* WDG_SW */
  4340. #define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /* nRST_STOP */
  4341. #define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /* nRST_STDBY */
  4342. #define FLASH_OBR_RAM_CODE_MOD ((uint16_t)0x0300)
  4343. #define FLASH_OBR_RAM_CODE_MOD_BIT1 ((uint16_t)0x0100)
  4344. #define FLASH_OBR_RAM_CODE_MOD_BIT2 ((uint16_t)0x0200)
  4345. /****************** Bit definition for FLASH_WPR register ******************/
  4346. #define FLASH_WPR_WRP ((uint32_t)0xFFFFFFFF) /* Write Protect */
  4347. /****************** Bit definition for FLASH_MODEKEYR register ******************/
  4348. #define FLASH_MODEKEYR_KEY1 ((uint32_t)0x45670123)
  4349. #define FLASH_MODEKEYR_KEY2 ((uint32_t)0xCDEF89AB)
  4350. /****************** Bit definition for FLASH_RDPR register *******************/
  4351. #define FLASH_RDPR_RDPR ((uint32_t)0x000000FF) /* Read protection option byte */
  4352. #define FLASH_RDPR_nRDPR ((uint32_t)0x0000FF00) /* Read protection complemented option byte */
  4353. /****************** Bit definition for FLASH_USER register ******************/
  4354. #define FLASH_USER_USER ((uint32_t)0x00FF0000) /* User option byte */
  4355. #define FLASH_USER_nUSER ((uint32_t)0xFF000000) /* User complemented option byte */
  4356. /****************** Bit definition for FLASH_Data0 register *****************/
  4357. #define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /* User data storage option byte */
  4358. #define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /* User data storage complemented option byte */
  4359. /****************** Bit definition for FLASH_Data1 register *****************/
  4360. #define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /* User data storage option byte */
  4361. #define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /* User data storage complemented option byte */
  4362. /****************** Bit definition for FLASH_WRPR0 register ******************/
  4363. #define FLASH_WRPR0_WRPR0 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */
  4364. #define FLASH_WRPR0_nWRPR0 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */
  4365. /****************** Bit definition for FLASH_WRPR1 register ******************/
  4366. #define FLASH_WRPR1_WRPR1 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */
  4367. #define FLASH_WRPR1_nWRPR1 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */
  4368. /****************** Bit definition for FLASH_WRPR2 register ******************/
  4369. #define FLASH_WRPR2_WRPR2 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */
  4370. #define FLASH_WRPR2_nWRPR2 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */
  4371. /****************** Bit definition for FLASH_WRPR3 register ******************/
  4372. #define FLASH_WRPR3_WRPR3 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */
  4373. #define FLASH_WRPR3_nWRPR3 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */
  4374. /******************************************************************************/
  4375. /* General Purpose and Alternate Function I/O */
  4376. /******************************************************************************/
  4377. /******************* Bit definition for GPIO_CFGLR register *******************/
  4378. #define GPIO_CFGLR_MODE ((uint32_t)0x33333333) /* Port x mode bits */
  4379. #define GPIO_CFGLR_MODE0 ((uint32_t)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */
  4380. #define GPIO_CFGLR_MODE0_0 ((uint32_t)0x00000001) /* Bit 0 */
  4381. #define GPIO_CFGLR_MODE0_1 ((uint32_t)0x00000002) /* Bit 1 */
  4382. #define GPIO_CFGLR_MODE1 ((uint32_t)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */
  4383. #define GPIO_CFGLR_MODE1_0 ((uint32_t)0x00000010) /* Bit 0 */
  4384. #define GPIO_CFGLR_MODE1_1 ((uint32_t)0x00000020) /* Bit 1 */
  4385. #define GPIO_CFGLR_MODE2 ((uint32_t)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */
  4386. #define GPIO_CFGLR_MODE2_0 ((uint32_t)0x00000100) /* Bit 0 */
  4387. #define GPIO_CFGLR_MODE2_1 ((uint32_t)0x00000200) /* Bit 1 */
  4388. #define GPIO_CFGLR_MODE3 ((uint32_t)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */
  4389. #define GPIO_CFGLR_MODE3_0 ((uint32_t)0x00001000) /* Bit 0 */
  4390. #define GPIO_CFGLR_MODE3_1 ((uint32_t)0x00002000) /* Bit 1 */
  4391. #define GPIO_CFGLR_MODE4 ((uint32_t)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */
  4392. #define GPIO_CFGLR_MODE4_0 ((uint32_t)0x00010000) /* Bit 0 */
  4393. #define GPIO_CFGLR_MODE4_1 ((uint32_t)0x00020000) /* Bit 1 */
  4394. #define GPIO_CFGLR_MODE5 ((uint32_t)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */
  4395. #define GPIO_CFGLR_MODE5_0 ((uint32_t)0x00100000) /* Bit 0 */
  4396. #define GPIO_CFGLR_MODE5_1 ((uint32_t)0x00200000) /* Bit 1 */
  4397. #define GPIO_CFGLR_MODE6 ((uint32_t)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */
  4398. #define GPIO_CFGLR_MODE6_0 ((uint32_t)0x01000000) /* Bit 0 */
  4399. #define GPIO_CFGLR_MODE6_1 ((uint32_t)0x02000000) /* Bit 1 */
  4400. #define GPIO_CFGLR_MODE7 ((uint32_t)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */
  4401. #define GPIO_CFGLR_MODE7_0 ((uint32_t)0x10000000) /* Bit 0 */
  4402. #define GPIO_CFGLR_MODE7_1 ((uint32_t)0x20000000) /* Bit 1 */
  4403. #define GPIO_CFGLR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */
  4404. #define GPIO_CFGLR_CNF0 ((uint32_t)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */
  4405. #define GPIO_CFGLR_CNF0_0 ((uint32_t)0x00000004) /* Bit 0 */
  4406. #define GPIO_CFGLR_CNF0_1 ((uint32_t)0x00000008) /* Bit 1 */
  4407. #define GPIO_CFGLR_CNF1 ((uint32_t)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */
  4408. #define GPIO_CFGLR_CNF1_0 ((uint32_t)0x00000040) /* Bit 0 */
  4409. #define GPIO_CFGLR_CNF1_1 ((uint32_t)0x00000080) /* Bit 1 */
  4410. #define GPIO_CFGLR_CNF2 ((uint32_t)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */
  4411. #define GPIO_CFGLR_CNF2_0 ((uint32_t)0x00000400) /* Bit 0 */
  4412. #define GPIO_CFGLR_CNF2_1 ((uint32_t)0x00000800) /* Bit 1 */
  4413. #define GPIO_CFGLR_CNF3 ((uint32_t)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */
  4414. #define GPIO_CFGLR_CNF3_0 ((uint32_t)0x00004000) /* Bit 0 */
  4415. #define GPIO_CFGLR_CNF3_1 ((uint32_t)0x00008000) /* Bit 1 */
  4416. #define GPIO_CFGLR_CNF4 ((uint32_t)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */
  4417. #define GPIO_CFGLR_CNF4_0 ((uint32_t)0x00040000) /* Bit 0 */
  4418. #define GPIO_CFGLR_CNF4_1 ((uint32_t)0x00080000) /* Bit 1 */
  4419. #define GPIO_CFGLR_CNF5 ((uint32_t)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */
  4420. #define GPIO_CFGLR_CNF5_0 ((uint32_t)0x00400000) /* Bit 0 */
  4421. #define GPIO_CFGLR_CNF5_1 ((uint32_t)0x00800000) /* Bit 1 */
  4422. #define GPIO_CFGLR_CNF6 ((uint32_t)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */
  4423. #define GPIO_CFGLR_CNF6_0 ((uint32_t)0x04000000) /* Bit 0 */
  4424. #define GPIO_CFGLR_CNF6_1 ((uint32_t)0x08000000) /* Bit 1 */
  4425. #define GPIO_CFGLR_CNF7 ((uint32_t)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */
  4426. #define GPIO_CFGLR_CNF7_0 ((uint32_t)0x40000000) /* Bit 0 */
  4427. #define GPIO_CFGLR_CNF7_1 ((uint32_t)0x80000000) /* Bit 1 */
  4428. /******************* Bit definition for GPIO_CFGHR register *******************/
  4429. #define GPIO_CFGHR_MODE ((uint32_t)0x33333333) /* Port x mode bits */
  4430. #define GPIO_CFGHR_MODE8 ((uint32_t)0x00000003) /* MODE8[1:0] bits (Port x mode bits, pin 8) */
  4431. #define GPIO_CFGHR_MODE8_0 ((uint32_t)0x00000001) /* Bit 0 */
  4432. #define GPIO_CFGHR_MODE8_1 ((uint32_t)0x00000002) /* Bit 1 */
  4433. #define GPIO_CFGHR_MODE9 ((uint32_t)0x00000030) /* MODE9[1:0] bits (Port x mode bits, pin 9) */
  4434. #define GPIO_CFGHR_MODE9_0 ((uint32_t)0x00000010) /* Bit 0 */
  4435. #define GPIO_CFGHR_MODE9_1 ((uint32_t)0x00000020) /* Bit 1 */
  4436. #define GPIO_CFGHR_MODE10 ((uint32_t)0x00000300) /* MODE10[1:0] bits (Port x mode bits, pin 10) */
  4437. #define GPIO_CFGHR_MODE10_0 ((uint32_t)0x00000100) /* Bit 0 */
  4438. #define GPIO_CFGHR_MODE10_1 ((uint32_t)0x00000200) /* Bit 1 */
  4439. #define GPIO_CFGHR_MODE11 ((uint32_t)0x00003000) /* MODE11[1:0] bits (Port x mode bits, pin 11) */
  4440. #define GPIO_CFGHR_MODE11_0 ((uint32_t)0x00001000) /* Bit 0 */
  4441. #define GPIO_CFGHR_MODE11_1 ((uint32_t)0x00002000) /* Bit 1 */
  4442. #define GPIO_CFGHR_MODE12 ((uint32_t)0x00030000) /* MODE12[1:0] bits (Port x mode bits, pin 12) */
  4443. #define GPIO_CFGHR_MODE12_0 ((uint32_t)0x00010000) /* Bit 0 */
  4444. #define GPIO_CFGHR_MODE12_1 ((uint32_t)0x00020000) /* Bit 1 */
  4445. #define GPIO_CFGHR_MODE13 ((uint32_t)0x00300000) /* MODE13[1:0] bits (Port x mode bits, pin 13) */
  4446. #define GPIO_CFGHR_MODE13_0 ((uint32_t)0x00100000) /* Bit 0 */
  4447. #define GPIO_CFGHR_MODE13_1 ((uint32_t)0x00200000) /* Bit 1 */
  4448. #define GPIO_CFGHR_MODE14 ((uint32_t)0x03000000) /* MODE14[1:0] bits (Port x mode bits, pin 14) */
  4449. #define GPIO_CFGHR_MODE14_0 ((uint32_t)0x01000000) /* Bit 0 */
  4450. #define GPIO_CFGHR_MODE14_1 ((uint32_t)0x02000000) /* Bit 1 */
  4451. #define GPIO_CFGHR_MODE15 ((uint32_t)0x30000000) /* MODE15[1:0] bits (Port x mode bits, pin 15) */
  4452. #define GPIO_CFGHR_MODE15_0 ((uint32_t)0x10000000) /* Bit 0 */
  4453. #define GPIO_CFGHR_MODE15_1 ((uint32_t)0x20000000) /* Bit 1 */
  4454. #define GPIO_CFGHR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */
  4455. #define GPIO_CFGHR_CNF8 ((uint32_t)0x0000000C) /* CNF8[1:0] bits (Port x configuration bits, pin 8) */
  4456. #define GPIO_CFGHR_CNF8_0 ((uint32_t)0x00000004) /* Bit 0 */
  4457. #define GPIO_CFGHR_CNF8_1 ((uint32_t)0x00000008) /* Bit 1 */
  4458. #define GPIO_CFGHR_CNF9 ((uint32_t)0x000000C0) /* CNF9[1:0] bits (Port x configuration bits, pin 9) */
  4459. #define GPIO_CFGHR_CNF9_0 ((uint32_t)0x00000040) /* Bit 0 */
  4460. #define GPIO_CFGHR_CNF9_1 ((uint32_t)0x00000080) /* Bit 1 */
  4461. #define GPIO_CFGHR_CNF10 ((uint32_t)0x00000C00) /* CNF10[1:0] bits (Port x configuration bits, pin 10) */
  4462. #define GPIO_CFGHR_CNF10_0 ((uint32_t)0x00000400) /* Bit 0 */
  4463. #define GPIO_CFGHR_CNF10_1 ((uint32_t)0x00000800) /* Bit 1 */
  4464. #define GPIO_CFGHR_CNF11 ((uint32_t)0x0000C000) /* CNF11[1:0] bits (Port x configuration bits, pin 11) */
  4465. #define GPIO_CFGHR_CNF11_0 ((uint32_t)0x00004000) /* Bit 0 */
  4466. #define GPIO_CFGHR_CNF11_1 ((uint32_t)0x00008000) /* Bit 1 */
  4467. #define GPIO_CFGHR_CNF12 ((uint32_t)0x000C0000) /* CNF12[1:0] bits (Port x configuration bits, pin 12) */
  4468. #define GPIO_CFGHR_CNF12_0 ((uint32_t)0x00040000) /* Bit 0 */
  4469. #define GPIO_CFGHR_CNF12_1 ((uint32_t)0x00080000) /* Bit 1 */
  4470. #define GPIO_CFGHR_CNF13 ((uint32_t)0x00C00000) /* CNF13[1:0] bits (Port x configuration bits, pin 13) */
  4471. #define GPIO_CFGHR_CNF13_0 ((uint32_t)0x00400000) /* Bit 0 */
  4472. #define GPIO_CFGHR_CNF13_1 ((uint32_t)0x00800000) /* Bit 1 */
  4473. #define GPIO_CFGHR_CNF14 ((uint32_t)0x0C000000) /* CNF14[1:0] bits (Port x configuration bits, pin 14) */
  4474. #define GPIO_CFGHR_CNF14_0 ((uint32_t)0x04000000) /* Bit 0 */
  4475. #define GPIO_CFGHR_CNF14_1 ((uint32_t)0x08000000) /* Bit 1 */
  4476. #define GPIO_CFGHR_CNF15 ((uint32_t)0xC0000000) /* CNF15[1:0] bits (Port x configuration bits, pin 15) */
  4477. #define GPIO_CFGHR_CNF15_0 ((uint32_t)0x40000000) /* Bit 0 */
  4478. #define GPIO_CFGHR_CNF15_1 ((uint32_t)0x80000000) /* Bit 1 */
  4479. /******************* Bit definition for GPIO_INDR register *******************/
  4480. #define GPIO_INDR_IDR0 ((uint16_t)0x0001) /* Port input data, bit 0 */
  4481. #define GPIO_INDR_IDR1 ((uint16_t)0x0002) /* Port input data, bit 1 */
  4482. #define GPIO_INDR_IDR2 ((uint16_t)0x0004) /* Port input data, bit 2 */
  4483. #define GPIO_INDR_IDR3 ((uint16_t)0x0008) /* Port input data, bit 3 */
  4484. #define GPIO_INDR_IDR4 ((uint16_t)0x0010) /* Port input data, bit 4 */
  4485. #define GPIO_INDR_IDR5 ((uint16_t)0x0020) /* Port input data, bit 5 */
  4486. #define GPIO_INDR_IDR6 ((uint16_t)0x0040) /* Port input data, bit 6 */
  4487. #define GPIO_INDR_IDR7 ((uint16_t)0x0080) /* Port input data, bit 7 */
  4488. #define GPIO_INDR_IDR8 ((uint16_t)0x0100) /* Port input data, bit 8 */
  4489. #define GPIO_INDR_IDR9 ((uint16_t)0x0200) /* Port input data, bit 9 */
  4490. #define GPIO_INDR_IDR10 ((uint16_t)0x0400) /* Port input data, bit 10 */
  4491. #define GPIO_INDR_IDR11 ((uint16_t)0x0800) /* Port input data, bit 11 */
  4492. #define GPIO_INDR_IDR12 ((uint16_t)0x1000) /* Port input data, bit 12 */
  4493. #define GPIO_INDR_IDR13 ((uint16_t)0x2000) /* Port input data, bit 13 */
  4494. #define GPIO_INDR_IDR14 ((uint16_t)0x4000) /* Port input data, bit 14 */
  4495. #define GPIO_INDR_IDR15 ((uint16_t)0x8000) /* Port input data, bit 15 */
  4496. /******************* Bit definition for GPIO_OUTDR register *******************/
  4497. #define GPIO_OUTDR_ODR0 ((uint16_t)0x0001) /* Port output data, bit 0 */
  4498. #define GPIO_OUTDR_ODR1 ((uint16_t)0x0002) /* Port output data, bit 1 */
  4499. #define GPIO_OUTDR_ODR2 ((uint16_t)0x0004) /* Port output data, bit 2 */
  4500. #define GPIO_OUTDR_ODR3 ((uint16_t)0x0008) /* Port output data, bit 3 */
  4501. #define GPIO_OUTDR_ODR4 ((uint16_t)0x0010) /* Port output data, bit 4 */
  4502. #define GPIO_OUTDR_ODR5 ((uint16_t)0x0020) /* Port output data, bit 5 */
  4503. #define GPIO_OUTDR_ODR6 ((uint16_t)0x0040) /* Port output data, bit 6 */
  4504. #define GPIO_OUTDR_ODR7 ((uint16_t)0x0080) /* Port output data, bit 7 */
  4505. #define GPIO_OUTDR_ODR8 ((uint16_t)0x0100) /* Port output data, bit 8 */
  4506. #define GPIO_OUTDR_ODR9 ((uint16_t)0x0200) /* Port output data, bit 9 */
  4507. #define GPIO_OUTDR_ODR10 ((uint16_t)0x0400) /* Port output data, bit 10 */
  4508. #define GPIO_OUTDR_ODR11 ((uint16_t)0x0800) /* Port output data, bit 11 */
  4509. #define GPIO_OUTDR_ODR12 ((uint16_t)0x1000) /* Port output data, bit 12 */
  4510. #define GPIO_OUTDR_ODR13 ((uint16_t)0x2000) /* Port output data, bit 13 */
  4511. #define GPIO_OUTDR_ODR14 ((uint16_t)0x4000) /* Port output data, bit 14 */
  4512. #define GPIO_OUTDR_ODR15 ((uint16_t)0x8000) /* Port output data, bit 15 */
  4513. /****************** Bit definition for GPIO_BSHR register *******************/
  4514. #define GPIO_BSHR_BS0 ((uint32_t)0x00000001) /* Port x Set bit 0 */
  4515. #define GPIO_BSHR_BS1 ((uint32_t)0x00000002) /* Port x Set bit 1 */
  4516. #define GPIO_BSHR_BS2 ((uint32_t)0x00000004) /* Port x Set bit 2 */
  4517. #define GPIO_BSHR_BS3 ((uint32_t)0x00000008) /* Port x Set bit 3 */
  4518. #define GPIO_BSHR_BS4 ((uint32_t)0x00000010) /* Port x Set bit 4 */
  4519. #define GPIO_BSHR_BS5 ((uint32_t)0x00000020) /* Port x Set bit 5 */
  4520. #define GPIO_BSHR_BS6 ((uint32_t)0x00000040) /* Port x Set bit 6 */
  4521. #define GPIO_BSHR_BS7 ((uint32_t)0x00000080) /* Port x Set bit 7 */
  4522. #define GPIO_BSHR_BS8 ((uint32_t)0x00000100) /* Port x Set bit 8 */
  4523. #define GPIO_BSHR_BS9 ((uint32_t)0x00000200) /* Port x Set bit 9 */
  4524. #define GPIO_BSHR_BS10 ((uint32_t)0x00000400) /* Port x Set bit 10 */
  4525. #define GPIO_BSHR_BS11 ((uint32_t)0x00000800) /* Port x Set bit 11 */
  4526. #define GPIO_BSHR_BS12 ((uint32_t)0x00001000) /* Port x Set bit 12 */
  4527. #define GPIO_BSHR_BS13 ((uint32_t)0x00002000) /* Port x Set bit 13 */
  4528. #define GPIO_BSHR_BS14 ((uint32_t)0x00004000) /* Port x Set bit 14 */
  4529. #define GPIO_BSHR_BS15 ((uint32_t)0x00008000) /* Port x Set bit 15 */
  4530. #define GPIO_BSHR_BR0 ((uint32_t)0x00010000) /* Port x Reset bit 0 */
  4531. #define GPIO_BSHR_BR1 ((uint32_t)0x00020000) /* Port x Reset bit 1 */
  4532. #define GPIO_BSHR_BR2 ((uint32_t)0x00040000) /* Port x Reset bit 2 */
  4533. #define GPIO_BSHR_BR3 ((uint32_t)0x00080000) /* Port x Reset bit 3 */
  4534. #define GPIO_BSHR_BR4 ((uint32_t)0x00100000) /* Port x Reset bit 4 */
  4535. #define GPIO_BSHR_BR5 ((uint32_t)0x00200000) /* Port x Reset bit 5 */
  4536. #define GPIO_BSHR_BR6 ((uint32_t)0x00400000) /* Port x Reset bit 6 */
  4537. #define GPIO_BSHR_BR7 ((uint32_t)0x00800000) /* Port x Reset bit 7 */
  4538. #define GPIO_BSHR_BR8 ((uint32_t)0x01000000) /* Port x Reset bit 8 */
  4539. #define GPIO_BSHR_BR9 ((uint32_t)0x02000000) /* Port x Reset bit 9 */
  4540. #define GPIO_BSHR_BR10 ((uint32_t)0x04000000) /* Port x Reset bit 10 */
  4541. #define GPIO_BSHR_BR11 ((uint32_t)0x08000000) /* Port x Reset bit 11 */
  4542. #define GPIO_BSHR_BR12 ((uint32_t)0x10000000) /* Port x Reset bit 12 */
  4543. #define GPIO_BSHR_BR13 ((uint32_t)0x20000000) /* Port x Reset bit 13 */
  4544. #define GPIO_BSHR_BR14 ((uint32_t)0x40000000) /* Port x Reset bit 14 */
  4545. #define GPIO_BSHR_BR15 ((uint32_t)0x80000000) /* Port x Reset bit 15 */
  4546. /******************* Bit definition for GPIO_BCR register *******************/
  4547. #define GPIO_BCR_BR0 ((uint16_t)0x0001) /* Port x Reset bit 0 */
  4548. #define GPIO_BCR_BR1 ((uint16_t)0x0002) /* Port x Reset bit 1 */
  4549. #define GPIO_BCR_BR2 ((uint16_t)0x0004) /* Port x Reset bit 2 */
  4550. #define GPIO_BCR_BR3 ((uint16_t)0x0008) /* Port x Reset bit 3 */
  4551. #define GPIO_BCR_BR4 ((uint16_t)0x0010) /* Port x Reset bit 4 */
  4552. #define GPIO_BCR_BR5 ((uint16_t)0x0020) /* Port x Reset bit 5 */
  4553. #define GPIO_BCR_BR6 ((uint16_t)0x0040) /* Port x Reset bit 6 */
  4554. #define GPIO_BCR_BR7 ((uint16_t)0x0080) /* Port x Reset bit 7 */
  4555. #define GPIO_BCR_BR8 ((uint16_t)0x0100) /* Port x Reset bit 8 */
  4556. #define GPIO_BCR_BR9 ((uint16_t)0x0200) /* Port x Reset bit 9 */
  4557. #define GPIO_BCR_BR10 ((uint16_t)0x0400) /* Port x Reset bit 10 */
  4558. #define GPIO_BCR_BR11 ((uint16_t)0x0800) /* Port x Reset bit 11 */
  4559. #define GPIO_BCR_BR12 ((uint16_t)0x1000) /* Port x Reset bit 12 */
  4560. #define GPIO_BCR_BR13 ((uint16_t)0x2000) /* Port x Reset bit 13 */
  4561. #define GPIO_BCR_BR14 ((uint16_t)0x4000) /* Port x Reset bit 14 */
  4562. #define GPIO_BCR_BR15 ((uint16_t)0x8000) /* Port x Reset bit 15 */
  4563. /****************** Bit definition for GPIO_LCKR register *******************/
  4564. #define GPIO_LCK0 ((uint32_t)0x00000001) /* Port x Lock bit 0 */
  4565. #define GPIO_LCK1 ((uint32_t)0x00000002) /* Port x Lock bit 1 */
  4566. #define GPIO_LCK2 ((uint32_t)0x00000004) /* Port x Lock bit 2 */
  4567. #define GPIO_LCK3 ((uint32_t)0x00000008) /* Port x Lock bit 3 */
  4568. #define GPIO_LCK4 ((uint32_t)0x00000010) /* Port x Lock bit 4 */
  4569. #define GPIO_LCK5 ((uint32_t)0x00000020) /* Port x Lock bit 5 */
  4570. #define GPIO_LCK6 ((uint32_t)0x00000040) /* Port x Lock bit 6 */
  4571. #define GPIO_LCK7 ((uint32_t)0x00000080) /* Port x Lock bit 7 */
  4572. #define GPIO_LCK8 ((uint32_t)0x00000100) /* Port x Lock bit 8 */
  4573. #define GPIO_LCK9 ((uint32_t)0x00000200) /* Port x Lock bit 9 */
  4574. #define GPIO_LCK10 ((uint32_t)0x00000400) /* Port x Lock bit 10 */
  4575. #define GPIO_LCK11 ((uint32_t)0x00000800) /* Port x Lock bit 11 */
  4576. #define GPIO_LCK12 ((uint32_t)0x00001000) /* Port x Lock bit 12 */
  4577. #define GPIO_LCK13 ((uint32_t)0x00002000) /* Port x Lock bit 13 */
  4578. #define GPIO_LCK14 ((uint32_t)0x00004000) /* Port x Lock bit 14 */
  4579. #define GPIO_LCK15 ((uint32_t)0x00008000) /* Port x Lock bit 15 */
  4580. #define GPIO_LCKK ((uint32_t)0x00010000) /* Lock key */
  4581. /****************** Bit definition for AFIO_ECR register *******************/
  4582. #define AFIO_ECR_PIN ((uint8_t)0x0F) /* PIN[3:0] bits (Pin selection) */
  4583. #define AFIO_ECR_PIN_0 ((uint8_t)0x01) /* Bit 0 */
  4584. #define AFIO_ECR_PIN_1 ((uint8_t)0x02) /* Bit 1 */
  4585. #define AFIO_ECR_PIN_2 ((uint8_t)0x04) /* Bit 2 */
  4586. #define AFIO_ECR_PIN_3 ((uint8_t)0x08) /* Bit 3 */
  4587. #define AFIO_ECR_PIN_PX0 ((uint8_t)0x00) /* Pin 0 selected */
  4588. #define AFIO_ECR_PIN_PX1 ((uint8_t)0x01) /* Pin 1 selected */
  4589. #define AFIO_ECR_PIN_PX2 ((uint8_t)0x02) /* Pin 2 selected */
  4590. #define AFIO_ECR_PIN_PX3 ((uint8_t)0x03) /* Pin 3 selected */
  4591. #define AFIO_ECR_PIN_PX4 ((uint8_t)0x04) /* Pin 4 selected */
  4592. #define AFIO_ECR_PIN_PX5 ((uint8_t)0x05) /* Pin 5 selected */
  4593. #define AFIO_ECR_PIN_PX6 ((uint8_t)0x06) /* Pin 6 selected */
  4594. #define AFIO_ECR_PIN_PX7 ((uint8_t)0x07) /* Pin 7 selected */
  4595. #define AFIO_ECR_PIN_PX8 ((uint8_t)0x08) /* Pin 8 selected */
  4596. #define AFIO_ECR_PIN_PX9 ((uint8_t)0x09) /* Pin 9 selected */
  4597. #define AFIO_ECR_PIN_PX10 ((uint8_t)0x0A) /* Pin 10 selected */
  4598. #define AFIO_ECR_PIN_PX11 ((uint8_t)0x0B) /* Pin 11 selected */
  4599. #define AFIO_ECR_PIN_PX12 ((uint8_t)0x0C) /* Pin 12 selected */
  4600. #define AFIO_ECR_PIN_PX13 ((uint8_t)0x0D) /* Pin 13 selected */
  4601. #define AFIO_ECR_PIN_PX14 ((uint8_t)0x0E) /* Pin 14 selected */
  4602. #define AFIO_ECR_PIN_PX15 ((uint8_t)0x0F) /* Pin 15 selected */
  4603. #define AFIO_ECR_PORT ((uint8_t)0x70) /* PORT[2:0] bits (Port selection) */
  4604. #define AFIO_ECR_PORT_0 ((uint8_t)0x10) /* Bit 0 */
  4605. #define AFIO_ECR_PORT_1 ((uint8_t)0x20) /* Bit 1 */
  4606. #define AFIO_ECR_PORT_2 ((uint8_t)0x40) /* Bit 2 */
  4607. #define AFIO_ECR_PORT_PA ((uint8_t)0x00) /* Port A selected */
  4608. #define AFIO_ECR_PORT_PB ((uint8_t)0x10) /* Port B selected */
  4609. #define AFIO_ECR_PORT_PC ((uint8_t)0x20) /* Port C selected */
  4610. #define AFIO_ECR_PORT_PD ((uint8_t)0x30) /* Port D selected */
  4611. #define AFIO_ECR_PORT_PE ((uint8_t)0x40) /* Port E selected */
  4612. #define AFIO_ECR_EVOE ((uint8_t)0x80) /* Event Output Enable */
  4613. /****************** Bit definition for AFIO_PCFR1register *******************/
  4614. #define AFIO_PCFR1_SPI1_REMAP ((uint32_t)0x00000001) /* SPI1 remapping */
  4615. #define AFIO_PCFR1_I2C1_REMAP ((uint32_t)0x00000002) /* I2C1 remapping */
  4616. #define AFIO_PCFR1_USART1_REMAP ((uint32_t)0x00000004) /* USART1 remapping */
  4617. #define AFIO_PCFR1_USART2_REMAP ((uint32_t)0x00000008) /* USART2 remapping */
  4618. #define AFIO_PCFR1_USART3_REMAP ((uint32_t)0x00000030) /* USART3_REMAP[1:0] bits (USART3 remapping) */
  4619. #define AFIO_PCFR1_USART3_REMAP_0 ((uint32_t)0x00000010) /* Bit 0 */
  4620. #define AFIO_PCFR1_USART3_REMAP_1 ((uint32_t)0x00000020) /* Bit 1 */
  4621. #define AFIO_PCFR1_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
  4622. #define AFIO_PCFR1_USART3_REMAP_PARTIALREMAP1 ((uint32_t)0x00000010) /* Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
  4623. #define AFIO_PCFR1_USART3_REMAP_PARTIALREMAP2 ((uint32_t)0x00000020)
  4624. #define AFIO_PCFR1_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /* Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
  4625. #define AFIO_PCFR1_TIM1_REMAP ((uint32_t)0x000000C0) /* TIM1_REMAP[1:0] bits (TIM1 remapping) */
  4626. #define AFIO_PCFR1_TIM1_REMAP_0 ((uint32_t)0x00000040) /* Bit 0 */
  4627. #define AFIO_PCFR1_TIM1_REMAP_1 ((uint32_t)0x00000080) /* Bit 1 */
  4628. #define AFIO_PCFR1_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
  4629. #define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /* Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
  4630. #define AFIO_PCFR1_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /* Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
  4631. #define AFIO_PCFR1_TIM2_REMAP ((uint32_t)0x00000300) /* TIM2_REMAP[1:0] bits (TIM2 remapping) */
  4632. #define AFIO_PCFR1_TIM2_REMAP_0 ((uint32_t)0x00000100) /* Bit 0 */
  4633. #define AFIO_PCFR1_TIM2_REMAP_1 ((uint32_t)0x00000200) /* Bit 1 */
  4634. #define AFIO_PCFR1_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
  4635. #define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /* Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
  4636. #define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /* Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
  4637. #define AFIO_PCFR1_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /* Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
  4638. #define AFIO_PCFR1_TIM3_REMAP ((uint32_t)0x00000C00) /* TIM3_REMAP[1:0] bits (TIM3 remapping) */
  4639. #define AFIO_PCFR1_TIM3_REMAP_0 ((uint32_t)0x00000400) /* Bit 0 */
  4640. #define AFIO_PCFR1_TIM3_REMAP_1 ((uint32_t)0x00000800) /* Bit 1 */
  4641. #define AFIO_PCFR1_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
  4642. #define AFIO_PCFR1_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /* Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
  4643. #define AFIO_PCFR1_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /* Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
  4644. #define AFIO_PCFR1_TIM4_REMAP ((uint32_t)0x00001000) /* TIM4_REMAP bit (TIM4 remapping) */
  4645. #define AFIO_PCFR1_CAN_REMAP ((uint32_t)0x00006000) /* CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
  4646. #define AFIO_PCFR1_CAN_REMAP_0 ((uint32_t)0x00002000) /* Bit 0 */
  4647. #define AFIO_PCFR1_CAN_REMAP_1 ((uint32_t)0x00004000) /* Bit 1 */
  4648. #define AFIO_PCFR1_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /* CANRX mapped to PA11, CANTX mapped to PA12 */
  4649. #define AFIO_PCFR1_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /* CANRX mapped to PB8, CANTX mapped to PB9 */
  4650. #define AFIO_PCFR1_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /* CANRX mapped to PD0, CANTX mapped to PD1 */
  4651. #define AFIO_PCFR1_PD01_REMAP ((uint32_t)0x00008000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
  4652. #define AFIO_PCFR1_TIM5CH4_IREMAP ((uint32_t)0x00010000) /* TIM5 Channel4 Internal Remap */
  4653. #define AFIO_PCFR1_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /* ADC 1 External Trigger Injected Conversion remapping */
  4654. #define AFIO_PCFR1_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /* ADC 1 External Trigger Regular Conversion remapping */
  4655. #define AFIO_PCFR1_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /* ADC 2 External Trigger Injected Conversion remapping */
  4656. #define AFIO_PCFR1_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /* ADC 2 External Trigger Regular Conversion remapping */
  4657. #define AFIO_PCFR1_ETH_REMAP ((uint32_t)0x00200000)
  4658. #define AFIO_PCFR1_CAN2_REMAP ((uint32_t)0x00400000)
  4659. #define AFIO_PCFR1_MII_RMII_REMAP ((uint32_t)0x00800000)
  4660. #define AFIO_PCFR1_SWJ_CFG ((uint32_t)0x07000000) /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
  4661. #define AFIO_PCFR1_SWJ_CFG_0 ((uint32_t)0x01000000) /* Bit 0 */
  4662. #define AFIO_PCFR1_SWJ_CFG_1 ((uint32_t)0x02000000) /* Bit 1 */
  4663. #define AFIO_PCFR1_SWJ_CFG_2 ((uint32_t)0x04000000) /* Bit 2 */
  4664. #define AFIO_PCFR1_SWJ_CFG_RESET ((uint32_t)0x00000000) /* Full SWJ (JTAG-DP + SW-DP) : Reset State */
  4665. #define AFIO_PCFR1_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /* Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
  4666. #define AFIO_PCFR1_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /* JTAG-DP Disabled and SW-DP Enabled */
  4667. #define AFIO_PCFR1_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /* JTAG-DP Disabled and SW-DP Disabled */
  4668. #define AFIO_PCFR1_SPI3_REMAP ((uint32_t)0x10000000)
  4669. #define AFIO_PCFR1_TIM2ITR1_REMAP ((uint32_t)0x20000000)
  4670. #define AFIO_PCFR1_PTP_PPS_REMAP ((uint32_t)0x40000000)
  4671. /***************** Bit definition for AFIO_EXTICR1 register *****************/
  4672. #define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /* EXTI 0 configuration */
  4673. #define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /* EXTI 1 configuration */
  4674. #define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /* EXTI 2 configuration */
  4675. #define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /* EXTI 3 configuration */
  4676. #define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /* PA[0] pin */
  4677. #define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /* PB[0] pin */
  4678. #define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /* PC[0] pin */
  4679. #define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /* PD[0] pin */
  4680. #define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /* PE[0] pin */
  4681. #define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /* PA[1] pin */
  4682. #define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /* PB[1] pin */
  4683. #define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /* PC[1] pin */
  4684. #define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /* PD[1] pin */
  4685. #define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /* PE[1] pin */
  4686. #define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /* PA[2] pin */
  4687. #define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /* PB[2] pin */
  4688. #define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /* PC[2] pin */
  4689. #define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /* PD[2] pin */
  4690. #define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /* PE[2] pin */
  4691. #define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /* PA[3] pin */
  4692. #define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /* PB[3] pin */
  4693. #define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /* PC[3] pin */
  4694. #define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /* PD[3] pin */
  4695. #define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /* PE[3] pin */
  4696. /***************** Bit definition for AFIO_EXTICR2 register *****************/
  4697. #define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /* EXTI 4 configuration */
  4698. #define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /* EXTI 5 configuration */
  4699. #define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /* EXTI 6 configuration */
  4700. #define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /* EXTI 7 configuration */
  4701. #define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /* PA[4] pin */
  4702. #define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /* PB[4] pin */
  4703. #define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /* PC[4] pin */
  4704. #define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /* PD[4] pin */
  4705. #define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /* PE[4] pin */
  4706. #define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /* PA[5] pin */
  4707. #define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /* PB[5] pin */
  4708. #define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /* PC[5] pin */
  4709. #define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /* PD[5] pin */
  4710. #define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /* PE[5] pin */
  4711. #define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /* PA[6] pin */
  4712. #define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /* PB[6] pin */
  4713. #define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /* PC[6] pin */
  4714. #define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /* PD[6] pin */
  4715. #define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /* PE[6] pin */
  4716. #define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /* PA[7] pin */
  4717. #define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /* PB[7] pin */
  4718. #define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /* PC[7] pin */
  4719. #define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /* PD[7] pin */
  4720. #define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /* PE[7] pin */
  4721. /***************** Bit definition for AFIO_EXTICR3 register *****************/
  4722. #define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /* EXTI 8 configuration */
  4723. #define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /* EXTI 9 configuration */
  4724. #define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /* EXTI 10 configuration */
  4725. #define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /* EXTI 11 configuration */
  4726. #define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /* PA[8] pin */
  4727. #define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /* PB[8] pin */
  4728. #define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /* PC[8] pin */
  4729. #define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /* PD[8] pin */
  4730. #define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /* PE[8] pin */
  4731. #define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /* PA[9] pin */
  4732. #define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /* PB[9] pin */
  4733. #define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /* PC[9] pin */
  4734. #define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /* PD[9] pin */
  4735. #define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /* PE[9] pin */
  4736. #define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /* PA[10] pin */
  4737. #define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /* PB[10] pin */
  4738. #define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /* PC[10] pin */
  4739. #define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /* PD[10] pin */
  4740. #define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /* PE[10] pin */
  4741. #define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /* PA[11] pin */
  4742. #define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /* PB[11] pin */
  4743. #define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /* PC[11] pin */
  4744. #define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /* PD[11] pin */
  4745. #define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /* PE[11] pin */
  4746. /***************** Bit definition for AFIO_EXTICR4 register *****************/
  4747. #define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /* EXTI 12 configuration */
  4748. #define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /* EXTI 13 configuration */
  4749. #define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /* EXTI 14 configuration */
  4750. #define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /* EXTI 15 configuration */
  4751. #define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /* PA[12] pin */
  4752. #define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /* PB[12] pin */
  4753. #define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /* PC[12] pin */
  4754. #define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /* PD[12] pin */
  4755. #define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /* PE[12] pin */
  4756. #define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /* PA[13] pin */
  4757. #define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /* PB[13] pin */
  4758. #define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /* PC[13] pin */
  4759. #define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /* PD[13] pin */
  4760. #define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /* PE[13] pin */
  4761. #define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /* PA[14] pin */
  4762. #define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /* PB[14] pin */
  4763. #define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /* PC[14] pin */
  4764. #define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /* PD[14] pin */
  4765. #define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /* PE[14] pin *//
  4766. #define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /* PA[15] pin */
  4767. #define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /* PB[15] pin */
  4768. #define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /* PC[15] pin */
  4769. #define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /* PD[15] pin */
  4770. #define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /* PE[15] pin */
  4771. /****************** Bit definition for AFIO_PCFR2register *******************/
  4772. #define AFIO_PCFR2_TIM8_REMAP ((uint32_t)0x00000004)
  4773. #define AFIO_PCFR2_TIM9_REMAP ((uint32_t)0x00000018)
  4774. #define AFIO_PCFR2_TIM9_REMAP_0 ((uint32_t)0x00000008)
  4775. #define AFIO_PCFR2_TIM9_REMAP_1 ((uint32_t)0x00000010)
  4776. #define AFIO_PCFR2_TIM9_REMAP_NOREMAP ((uint32_t)0x00000000)
  4777. #define AFIO_PCFR2_TIM9_REMAP_PARTIALREMAP ((uint32_t)0x00000008)
  4778. #define AFIO_PCFR2_TIM9_REMAP_FULLREMAP ((uint32_t)0x00000010)
  4779. #define AFIO_PCFR2_TIM10_REMAP ((uint32_t)0x00000060)
  4780. #define AFIO_PCFR2_TIM10_REMAP_0 ((uint32_t)0x00000020)
  4781. #define AFIO_PCFR2_TIM10_REMAP_1 ((uint32_t)0x00000040)
  4782. #define AFIO_PCFR2_TIM10_REMAP_NOREMAP ((uint32_t)0x00000000)
  4783. #define AFIO_PCFR2_TIM10_REMAP_PARTIALREMAP ((uint32_t)0x00000020)
  4784. #define AFIO_PCFR2_TIM10_REMAP_FULLREMAP ((uint32_t)0x00000040)
  4785. #define AFIO_PCFR2_FSMC_NADV_REMAP ((uint32_t)0x00000400)
  4786. #define AFIO_PCFR2_USART4_REMAP ((uint32_t)0x00030000)
  4787. #define AFIO_PCFR2_USART4_REMAP_0 ((uint32_t)0x00010000)
  4788. #define AFIO_PCFR2_USART4_REMAP_1 ((uint32_t)0x00020000)
  4789. #define AFIO_PCFR2_USART4_REMAP_NOREMAP ((uint32_t)0x00000000)
  4790. #define AFIO_PCFR2_USART4_REMAP_PARTIALREMAP ((uint32_t)0x00010000)
  4791. #define AFIO_PCFR2_USART4_REMAP_FULLREMAP ((uint32_t)0x00020000)
  4792. #define AFIO_PCFR2_USART5_REMAP ((uint32_t)0x000C0000)
  4793. #define AFIO_PCFR2_USART5_REMAP_0 ((uint32_t)0x00040000)
  4794. #define AFIO_PCFR2_USART5_REMAP_1 ((uint32_t)0x00080000)
  4795. #define AFIO_PCFR2_USART5_REMAP_NOREMAP ((uint32_t)0x00000000)
  4796. #define AFIO_PCFR2_USART5_REMAP_PARTIALREMAP ((uint32_t)0x00040000)
  4797. #define AFIO_PCFR2_USART5_REMAP_FULLREMAP ((uint32_t)0x00080000)
  4798. #define AFIO_PCFR2_USART6_REMAP ((uint32_t)0x00300000)
  4799. #define AFIO_PCFR2_USART6_REMAP_0 ((uint32_t)0x00100000)
  4800. #define AFIO_PCFR2_USART6_REMAP_1 ((uint32_t)0x00200000)
  4801. #define AFIO_PCFR2_USART6_REMAP_NOREMAP ((uint32_t)0x00000000)
  4802. #define AFIO_PCFR2_USART6_REMAP_PARTIALREMAP ((uint32_t)0x00100000)
  4803. #define AFIO_PCFR2_USART6_REMAP_FULLREMAP ((uint32_t)0x00200000)
  4804. #define AFIO_PCFR2_USART7_REMAP ((uint32_t)0x00C00000)
  4805. #define AFIO_PCFR2_USART7_REMAP_0 ((uint32_t)0x00400000)
  4806. #define AFIO_PCFR2_USART7_REMAP_1 ((uint32_t)0x00800000)
  4807. #define AFIO_PCFR2_USART7_REMAP_NOREMAP ((uint32_t)0x00000000)
  4808. #define AFIO_PCFR2_USART7_REMAP_PARTIALREMAP ((uint32_t)0x00400000)
  4809. #define AFIO_PCFR2_USART7_REMAP_FULLREMAP ((uint32_t)0x00800000)
  4810. #define AFIO_PCFR2_USART8_REMAP ((uint32_t)0x03000000)
  4811. #define AFIO_PCFR2_USART8_REMAP_0 ((uint32_t)0x01000000)
  4812. #define AFIO_PCFR2_USART8_REMAP_1 ((uint32_t)0x02000000)
  4813. #define AFIO_PCFR2_USART8_REMAP_NOREMAP ((uint32_t)0x00000000)
  4814. #define AFIO_PCFR2_USART8_REMAP_PARTIALREMAP ((uint32_t)0x01000000)
  4815. #define AFIO_PCFR2_USART8_REMAP_FULLREMAP ((uint32_t)0x02000000)
  4816. #define AFIO_PCFR2_USART1_REMAP ((uint32_t)0x04000000)
  4817. /******************************************************************************/
  4818. /* Independent WATCHDOG */
  4819. /******************************************************************************/
  4820. /******************* Bit definition for IWDG_CTLR register ********************/
  4821. #define IWDG_KEY ((uint16_t)0xFFFF) /* Key value (write only, read 0000h) */
  4822. /******************* Bit definition for IWDG_PSCR register ********************/
  4823. #define IWDG_PR ((uint8_t)0x07) /* PR[2:0] (Prescaler divider) */
  4824. #define IWDG_PR_0 ((uint8_t)0x01) /* Bit 0 */
  4825. #define IWDG_PR_1 ((uint8_t)0x02) /* Bit 1 */
  4826. #define IWDG_PR_2 ((uint8_t)0x04) /* Bit 2 */
  4827. /******************* Bit definition for IWDG_RLDR register *******************/
  4828. #define IWDG_RL ((uint16_t)0x0FFF) /* Watchdog counter reload value */
  4829. /******************* Bit definition for IWDG_STATR register ********************/
  4830. #define IWDG_PVU ((uint8_t)0x01) /* Watchdog prescaler value update */
  4831. #define IWDG_RVU ((uint8_t)0x02) /* Watchdog counter reload value update */
  4832. /******************************************************************************/
  4833. /* Inter-integrated Circuit Interface */
  4834. /******************************************************************************/
  4835. /******************* Bit definition for I2C_CTLR1 register ********************/
  4836. #define I2C_CTLR1_PE ((uint16_t)0x0001) /* Peripheral Enable */
  4837. #define I2C_CTLR1_SMBUS ((uint16_t)0x0002) /* SMBus Mode */
  4838. #define I2C_CTLR1_SMBTYPE ((uint16_t)0x0008) /* SMBus Type */
  4839. #define I2C_CTLR1_ENARP ((uint16_t)0x0010) /* ARP Enable */
  4840. #define I2C_CTLR1_ENPEC ((uint16_t)0x0020) /* PEC Enable */
  4841. #define I2C_CTLR1_ENGC ((uint16_t)0x0040) /* General Call Enable */
  4842. #define I2C_CTLR1_NOSTRETCH ((uint16_t)0x0080) /* Clock Stretching Disable (Slave mode) */
  4843. #define I2C_CTLR1_START ((uint16_t)0x0100) /* Start Generation */
  4844. #define I2C_CTLR1_STOP ((uint16_t)0x0200) /* Stop Generation */
  4845. #define I2C_CTLR1_ACK ((uint16_t)0x0400) /* Acknowledge Enable */
  4846. #define I2C_CTLR1_POS ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */
  4847. #define I2C_CTLR1_PEC ((uint16_t)0x1000) /* Packet Error Checking */
  4848. #define I2C_CTLR1_ALERT ((uint16_t)0x2000) /* SMBus Alert */
  4849. #define I2C_CTLR1_SWRST ((uint16_t)0x8000) /* Software Reset */
  4850. /******************* Bit definition for I2C_CTLR2 register ********************/
  4851. #define I2C_CTLR2_FREQ ((uint16_t)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */
  4852. #define I2C_CTLR2_FREQ_0 ((uint16_t)0x0001) /* Bit 0 */
  4853. #define I2C_CTLR2_FREQ_1 ((uint16_t)0x0002) /* Bit 1 */
  4854. #define I2C_CTLR2_FREQ_2 ((uint16_t)0x0004) /* Bit 2 */
  4855. #define I2C_CTLR2_FREQ_3 ((uint16_t)0x0008) /* Bit 3 */
  4856. #define I2C_CTLR2_FREQ_4 ((uint16_t)0x0010) /* Bit 4 */
  4857. #define I2C_CTLR2_FREQ_5 ((uint16_t)0x0020) /* Bit 5 */
  4858. #define I2C_CTLR2_ITERREN ((uint16_t)0x0100) /* Error Interrupt Enable */
  4859. #define I2C_CTLR2_ITEVTEN ((uint16_t)0x0200) /* Event Interrupt Enable */
  4860. #define I2C_CTLR2_ITBUFEN ((uint16_t)0x0400) /* Buffer Interrupt Enable */
  4861. #define I2C_CTLR2_DMAEN ((uint16_t)0x0800) /* DMA Requests Enable */
  4862. #define I2C_CTLR2_LAST ((uint16_t)0x1000) /* DMA Last Transfer */
  4863. /******************* Bit definition for I2C_OADDR1 register *******************/
  4864. #define I2C_OADDR1_ADD0 ((uint16_t)0x0001)
  4865. #define I2C_OADDR1_ADD1_7 ((uint16_t)0x00FE) /* Interface Address */
  4866. #define I2C_OADDR1_ADD8_9 ((uint16_t)0x0300) /* Interface Address */
  4867. #define I2C_OADDR1_ADD0 ((uint16_t)0x0001) /* Bit 0 */
  4868. #define I2C_OADDR1_ADD1 ((uint16_t)0x0002) /* Bit 1 */
  4869. #define I2C_OADDR1_ADD2 ((uint16_t)0x0004) /* Bit 2 */
  4870. #define I2C_OADDR1_ADD3 ((uint16_t)0x0008) /* Bit 3 */
  4871. #define I2C_OADDR1_ADD4 ((uint16_t)0x0010) /* Bit 4 */
  4872. #define I2C_OADDR1_ADD5 ((uint16_t)0x0020) /* Bit 5 */
  4873. #define I2C_OADDR1_ADD6 ((uint16_t)0x0040) /* Bit 6 */
  4874. #define I2C_OADDR1_ADD7 ((uint16_t)0x0080) /* Bit 7 */
  4875. #define I2C_OADDR1_ADD8 ((uint16_t)0x0100) /* Bit 8 */
  4876. #define I2C_OADDR1_ADD9 ((uint16_t)0x0200) /* Bit 9 */
  4877. #define I2C_OADDR1_ADDMODE ((uint16_t)0x8000) /* Addressing Mode (Slave mode) */
  4878. /******************* Bit definition for I2C_OADDR2 register *******************/
  4879. #define I2C_OADDR2_ENDUAL ((uint8_t)0x01) /* Dual addressing mode enable */
  4880. #define I2C_OADDR2_ADD2 ((uint8_t)0xFE) /* Interface address */
  4881. /******************** Bit definition for I2C_DATAR register ********************/
  4882. #define I2C_DR_DATAR ((uint8_t)0xFF) /* 8-bit Data Register */
  4883. /******************* Bit definition for I2C_STAR1 register ********************/
  4884. #define I2C_STAR1_SB ((uint16_t)0x0001) /* Start Bit (Master mode) */
  4885. #define I2C_STAR1_ADDR ((uint16_t)0x0002) /* Address sent (master mode)/matched (slave mode) */
  4886. #define I2C_STAR1_BTF ((uint16_t)0x0004) /* Byte Transfer Finished */
  4887. #define I2C_STAR1_ADD10 ((uint16_t)0x0008) /* 10-bit header sent (Master mode) */
  4888. #define I2C_STAR1_STOPF ((uint16_t)0x0010) /* Stop detection (Slave mode) */
  4889. #define I2C_STAR1_RXNE ((uint16_t)0x0040) /* Data Register not Empty (receivers) */
  4890. #define I2C_STAR1_TXE ((uint16_t)0x0080) /* Data Register Empty (transmitters) */
  4891. #define I2C_STAR1_BERR ((uint16_t)0x0100) /* Bus Error */
  4892. #define I2C_STAR1_ARLO ((uint16_t)0x0200) /* Arbitration Lost (master mode) */
  4893. #define I2C_STAR1_AF ((uint16_t)0x0400) /* Acknowledge Failure */
  4894. #define I2C_STAR1_OVR ((uint16_t)0x0800) /* Overrun/Underrun */
  4895. #define I2C_STAR1_PECERR ((uint16_t)0x1000) /* PEC Error in reception */
  4896. #define I2C_STAR1_TIMEOUT ((uint16_t)0x4000) /* Timeout or Tlow Error */
  4897. #define I2C_STAR1_SMBALERT ((uint16_t)0x8000) /* SMBus Alert */
  4898. /******************* Bit definition for I2C_STAR2 register ********************/
  4899. #define I2C_STAR2_MSL ((uint16_t)0x0001) /* Master/Slave */
  4900. #define I2C_STAR2_BUSY ((uint16_t)0x0002) /* Bus Busy */
  4901. #define I2C_STAR2_TRA ((uint16_t)0x0004) /* Transmitter/Receiver */
  4902. #define I2C_STAR2_GENCALL ((uint16_t)0x0010) /* General Call Address (Slave mode) */
  4903. #define I2C_STAR2_SMBDEFAULT ((uint16_t)0x0020) /* SMBus Device Default Address (Slave mode) */
  4904. #define I2C_STAR2_SMBHOST ((uint16_t)0x0040) /* SMBus Host Header (Slave mode) */
  4905. #define I2C_STAR2_DUALF ((uint16_t)0x0080) /* Dual Flag (Slave mode) */
  4906. #define I2C_STAR2_PEC ((uint16_t)0xFF00) /* Packet Error Checking Register */
  4907. /******************* Bit definition for I2C_CKCFGR register ********************/
  4908. #define I2C_CKCFGR_CCR ((uint16_t)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */
  4909. #define I2C_CKCFGR_DUTY ((uint16_t)0x4000) /* Fast Mode Duty Cycle */
  4910. #define I2C_CKCFGR_FS ((uint16_t)0x8000) /* I2C Master Mode Selection */
  4911. /****************** Bit definition for I2C_RTR register *******************/
  4912. #define I2C_RTR_TRISE ((uint8_t)0x3F) /* Maximum Rise Time in Fast/Standard mode (Master mode) */
  4913. /******************************************************************************/
  4914. /* Power Control */
  4915. /******************************************************************************/
  4916. /******************** Bit definition for PWR_CTLR register ********************/
  4917. #define PWR_CTLR_LPDS ((uint16_t)0x0001) /* Low-Power Deepsleep */
  4918. #define PWR_CTLR_PDDS ((uint16_t)0x0002) /* Power Down Deepsleep */
  4919. #define PWR_CTLR_CWUF ((uint16_t)0x0004) /* Clear Wakeup Flag */
  4920. #define PWR_CTLR_CSBF ((uint16_t)0x0008) /* Clear Standby Flag */
  4921. #define PWR_CTLR_PVDE ((uint16_t)0x0010) /* Power Voltage Detector Enable */
  4922. #define PWR_CTLR_PLS ((uint16_t)0x00E0) /* PLS[2:0] bits (PVD Level Selection) */
  4923. #define PWR_CTLR_PLS_0 ((uint16_t)0x0020) /* Bit 0 */
  4924. #define PWR_CTLR_PLS_1 ((uint16_t)0x0040) /* Bit 1 */
  4925. #define PWR_CTLR_PLS_2 ((uint16_t)0x0080) /* Bit 2 */
  4926. #define PWR_CTLR_PLS_MODE0 ((uint16_t)0x0000)
  4927. #define PWR_CTLR_PLS_MODE1 ((uint16_t)0x0020)
  4928. #define PWR_CTLR_PLS_MODE2 ((uint16_t)0x0040)
  4929. #define PWR_CTLR_PLS_MODE3 ((uint16_t)0x0060)
  4930. #define PWR_CTLR_PLS_MODE4 ((uint16_t)0x0080)
  4931. #define PWR_CTLR_PLS_MODE5 ((uint16_t)0x00A0)
  4932. #define PWR_CTLR_PLS_MODE6 ((uint16_t)0x00C0)
  4933. #define PWR_CTLR_PLS_MODE7 ((uint16_t)0x00E0)
  4934. #define PWR_CTLR_PLS_2V2 PWR_CTLR_PLS_MODE0
  4935. #define PWR_CTLR_PLS_2V3 PWR_CTLR_PLS_MODE1
  4936. #define PWR_CTLR_PLS_2V4 PWR_CTLR_PLS_MODE2
  4937. #define PWR_CTLR_PLS_2V5 PWR_CTLR_PLS_MODE3
  4938. #define PWR_CTLR_PLS_2V6 PWR_CTLR_PLS_MODE4
  4939. #define PWR_CTLR_PLS_2V7 PWR_CTLR_PLS_MODE5
  4940. #define PWR_CTLR_PLS_2V8 PWR_CTLR_PLS_MODE6
  4941. #define PWR_CTLR_PLS_2V9 PWR_CTLR_PLS_MODE7
  4942. #define PWR_CTLR_DBP ((uint16_t)0x0100) /* Disable Backup Domain write protection */
  4943. #define PWR_CTLR_R2KSTY ((uint32_t)0x10000)
  4944. #define PWR_CTLR_R30KSTY ((uint32_t)0x20000)
  4945. #define PWR_CTLR_R2KVBAT ((uint32_t)0x40000)
  4946. #define PWR_CTLR_R30KVBAT ((uint32_t)0x80000)
  4947. #define PWR_CTLR_RAMLV ((uint32_t)0x100000)
  4948. /******************* Bit definition for PWR_CSR register ********************/
  4949. #define PWR_CSR_WUF ((uint16_t)0x0001) /* Wakeup Flag */
  4950. #define PWR_CSR_SBF ((uint16_t)0x0002) /* Standby Flag */
  4951. #define PWR_CSR_PVDO ((uint16_t)0x0004) /* PVD Output */
  4952. #define PWR_CSR_EWUP ((uint16_t)0x0100) /* Enable WKUP pin */
  4953. /******************************************************************************/
  4954. /* Reset and Clock Control */
  4955. /******************************************************************************/
  4956. /******************** Bit definition for RCC_CTLR register ********************/
  4957. #define RCC_HSION ((uint32_t)0x00000001) /* Internal High Speed clock enable */
  4958. #define RCC_HSIRDY ((uint32_t)0x00000002) /* Internal High Speed clock ready flag */
  4959. #define RCC_HSITRIM ((uint32_t)0x000000F8) /* Internal High Speed clock trimming */
  4960. #define RCC_HSICAL ((uint32_t)0x0000FF00) /* Internal High Speed clock Calibration */
  4961. #define RCC_HSEON ((uint32_t)0x00010000) /* External High Speed clock enable */
  4962. #define RCC_HSERDY ((uint32_t)0x00020000) /* External High Speed clock ready flag */
  4963. #define RCC_HSEBYP ((uint32_t)0x00040000) /* External High Speed clock Bypass */
  4964. #define RCC_CSSON ((uint32_t)0x00080000) /* Clock Security System enable */
  4965. #define RCC_PLLON ((uint32_t)0x01000000) /* PLL enable */
  4966. #define RCC_PLLRDY ((uint32_t)0x02000000) /* PLL clock ready flag */
  4967. #define RCC_PLL2ON ((uint32_t)0x04000000)
  4968. #define RCC_PLL2RDY ((uint32_t)0x08000000)
  4969. #define RCC_PLL3ON ((uint32_t)0x10000000)
  4970. #define RCC_PLL3RDY ((uint32_t)0x20000000)
  4971. /******************* Bit definition for RCC_CFGR0 register *******************/
  4972. #define RCC_SW ((uint32_t)0x00000003) /* SW[1:0] bits (System clock Switch) */
  4973. #define RCC_SW_0 ((uint32_t)0x00000001) /* Bit 0 */
  4974. #define RCC_SW_1 ((uint32_t)0x00000002) /* Bit 1 */
  4975. #define RCC_SW_HSI ((uint32_t)0x00000000) /* HSI selected as system clock */
  4976. #define RCC_SW_HSE ((uint32_t)0x00000001) /* HSE selected as system clock */
  4977. #define RCC_SW_PLL ((uint32_t)0x00000002) /* PLL selected as system clock */
  4978. #define RCC_SWS ((uint32_t)0x0000000C) /* SWS[1:0] bits (System Clock Switch Status) */
  4979. #define RCC_SWS_0 ((uint32_t)0x00000004) /* Bit 0 */
  4980. #define RCC_SWS_1 ((uint32_t)0x00000008) /* Bit 1 */
  4981. #define RCC_SWS_HSI ((uint32_t)0x00000000) /* HSI oscillator used as system clock */
  4982. #define RCC_SWS_HSE ((uint32_t)0x00000004) /* HSE oscillator used as system clock */
  4983. #define RCC_SWS_PLL ((uint32_t)0x00000008) /* PLL used as system clock */
  4984. #define RCC_HPRE ((uint32_t)0x000000F0) /* HPRE[3:0] bits (AHB prescaler) */
  4985. #define RCC_HPRE_0 ((uint32_t)0x00000010) /* Bit 0 */
  4986. #define RCC_HPRE_1 ((uint32_t)0x00000020) /* Bit 1 */
  4987. #define RCC_HPRE_2 ((uint32_t)0x00000040) /* Bit 2 */
  4988. #define RCC_HPRE_3 ((uint32_t)0x00000080) /* Bit 3 */
  4989. #define RCC_HPRE_DIV1 ((uint32_t)0x00000000) /* SYSCLK not divided */
  4990. #define RCC_HPRE_DIV2 ((uint32_t)0x00000080) /* SYSCLK divided by 2 */
  4991. #define RCC_HPRE_DIV4 ((uint32_t)0x00000090) /* SYSCLK divided by 4 */
  4992. #define RCC_HPRE_DIV8 ((uint32_t)0x000000A0) /* SYSCLK divided by 8 */
  4993. #define RCC_HPRE_DIV16 ((uint32_t)0x000000B0) /* SYSCLK divided by 16 */
  4994. #define RCC_HPRE_DIV64 ((uint32_t)0x000000C0) /* SYSCLK divided by 64 */
  4995. #define RCC_HPRE_DIV128 ((uint32_t)0x000000D0) /* SYSCLK divided by 128 */
  4996. #define RCC_HPRE_DIV256 ((uint32_t)0x000000E0) /* SYSCLK divided by 256 */
  4997. #define RCC_HPRE_DIV512 ((uint32_t)0x000000F0) /* SYSCLK divided by 512 */
  4998. #define RCC_PPRE1 ((uint32_t)0x00000700) /* PRE1[2:0] bits (APB1 prescaler) */
  4999. #define RCC_PPRE1_0 ((uint32_t)0x00000100) /* Bit 0 */
  5000. #define RCC_PPRE1_1 ((uint32_t)0x00000200) /* Bit 1 */
  5001. #define RCC_PPRE1_2 ((uint32_t)0x00000400) /* Bit 2 */
  5002. #define RCC_PPRE1_DIV1 ((uint32_t)0x00000000) /* HCLK not divided */
  5003. #define RCC_PPRE1_DIV2 ((uint32_t)0x00000400) /* HCLK divided by 2 */
  5004. #define RCC_PPRE1_DIV4 ((uint32_t)0x00000500) /* HCLK divided by 4 */
  5005. #define RCC_PPRE1_DIV8 ((uint32_t)0x00000600) /* HCLK divided by 8 */
  5006. #define RCC_PPRE1_DIV16 ((uint32_t)0x00000700) /* HCLK divided by 16 */
  5007. #define RCC_PPRE2 ((uint32_t)0x00003800) /* PRE2[2:0] bits (APB2 prescaler) */
  5008. #define RCC_PPRE2_0 ((uint32_t)0x00000800) /* Bit 0 */
  5009. #define RCC_PPRE2_1 ((uint32_t)0x00001000) /* Bit 1 */
  5010. #define RCC_PPRE2_2 ((uint32_t)0x00002000) /* Bit 2 */
  5011. #define RCC_PPRE2_DIV1 ((uint32_t)0x00000000) /* HCLK not divided */
  5012. #define RCC_PPRE2_DIV2 ((uint32_t)0x00002000) /* HCLK divided by 2 */
  5013. #define RCC_PPRE2_DIV4 ((uint32_t)0x00002800) /* HCLK divided by 4 */
  5014. #define RCC_PPRE2_DIV8 ((uint32_t)0x00003000) /* HCLK divided by 8 */
  5015. #define RCC_PPRE2_DIV16 ((uint32_t)0x00003800) /* HCLK divided by 16 */
  5016. #define RCC_ADCPRE ((uint32_t)0x0000C000) /* ADCPRE[1:0] bits (ADC prescaler) */
  5017. #define RCC_ADCPRE_0 ((uint32_t)0x00004000) /* Bit 0 */
  5018. #define RCC_ADCPRE_1 ((uint32_t)0x00008000) /* Bit 1 */
  5019. #define RCC_ADCPRE_DIV2 ((uint32_t)0x00000000) /* PCLK2 divided by 2 */
  5020. #define RCC_ADCPRE_DIV4 ((uint32_t)0x00004000) /* PCLK2 divided by 4 */
  5021. #define RCC_ADCPRE_DIV6 ((uint32_t)0x00008000) /* PCLK2 divided by 6 */
  5022. #define RCC_ADCPRE_DIV8 ((uint32_t)0x0000C000) /* PCLK2 divided by 8 */
  5023. #define RCC_PLLSRC ((uint32_t)0x00010000) /* PLL entry clock source */
  5024. #define RCC_PLLXTPRE ((uint32_t)0x00020000) /* HSE divider for PLL entry */
  5025. #define RCC_PLLMULL ((uint32_t)0x003C0000) /* PLLMUL[3:0] bits (PLL multiplication factor) */
  5026. #define RCC_PLLMULL_0 ((uint32_t)0x00040000) /* Bit 0 */
  5027. #define RCC_PLLMULL_1 ((uint32_t)0x00080000) /* Bit 1 */
  5028. #define RCC_PLLMULL_2 ((uint32_t)0x00100000) /* Bit 2 */
  5029. #define RCC_PLLMULL_3 ((uint32_t)0x00200000) /* Bit 3 */
  5030. #define RCC_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /* HSI clock divided by 2 selected as PLL entry clock source */
  5031. #define RCC_PLLSRC_HSE ((uint32_t)0x00010000) /* HSE clock selected as PLL entry clock source */
  5032. #define RCC_PLLXTPRE_HSE ((uint32_t)0x00000000) /* HSE clock not divided for PLL entry */
  5033. #define RCC_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /* HSE clock divided by 2 for PLL entry */
  5034. /* CH32V303x */
  5035. #define RCC_PLLMULL2 ((uint32_t)0x00000000) /* PLL input clock*2 */
  5036. #define RCC_PLLMULL3 ((uint32_t)0x00040000) /* PLL input clock*3 */
  5037. #define RCC_PLLMULL4 ((uint32_t)0x00080000) /* PLL input clock*4 */
  5038. #define RCC_PLLMULL5 ((uint32_t)0x000C0000) /* PLL input clock*5 */
  5039. #define RCC_PLLMULL6 ((uint32_t)0x00100000) /* PLL input clock*6 */
  5040. #define RCC_PLLMULL7 ((uint32_t)0x00140000) /* PLL input clock*7 */
  5041. #define RCC_PLLMULL8 ((uint32_t)0x00180000) /* PLL input clock*8 */
  5042. #define RCC_PLLMULL9 ((uint32_t)0x001C0000) /* PLL input clock*9 */
  5043. #define RCC_PLLMULL10 ((uint32_t)0x00200000) /* PLL input clock10 */
  5044. #define RCC_PLLMULL11 ((uint32_t)0x00240000) /* PLL input clock*11 */
  5045. #define RCC_PLLMULL12 ((uint32_t)0x00280000) /* PLL input clock*12 */
  5046. #define RCC_PLLMULL13 ((uint32_t)0x002C0000) /* PLL input clock*13 */
  5047. #define RCC_PLLMULL14 ((uint32_t)0x00300000) /* PLL input clock*14 */
  5048. #define RCC_PLLMULL15 ((uint32_t)0x00340000) /* PLL input clock*15 */
  5049. #define RCC_PLLMULL16 ((uint32_t)0x00380000) /* PLL input clock*16 */
  5050. #define RCC_PLLMULL18 ((uint32_t)0x003C0000) /* PLL input clock*18 */
  5051. /* CH32V307x-CH32V305x */
  5052. #define RCC_PLLMULL18_EXTEN ((uint32_t)0x00000000) /* PLL input clock*18 */
  5053. #define RCC_PLLMULL3_EXTEN ((uint32_t)0x00040000) /* PLL input clock*3 */
  5054. #define RCC_PLLMULL4_EXTEN ((uint32_t)0x00080000) /* PLL input clock*4 */
  5055. #define RCC_PLLMULL5_EXTEN ((uint32_t)0x000C0000) /* PLL input clock*5 */
  5056. #define RCC_PLLMULL6_EXTEN ((uint32_t)0x00100000) /* PLL input clock*6 */
  5057. #define RCC_PLLMULL7_EXTEN ((uint32_t)0x00140000) /* PLL input clock*7 */
  5058. #define RCC_PLLMULL8_EXTEN ((uint32_t)0x00180000) /* PLL input clock*8 */
  5059. #define RCC_PLLMULL9_EXTEN ((uint32_t)0x001C0000) /* PLL input clock*9 */
  5060. #define RCC_PLLMULL10_EXTEN ((uint32_t)0x00200000) /* PLL input clock10 */
  5061. #define RCC_PLLMULL11_EXTEN ((uint32_t)0x00240000) /* PLL input clock*11 */
  5062. #define RCC_PLLMULL12_EXTEN ((uint32_t)0x00280000) /* PLL input clock*12 */
  5063. #define RCC_PLLMULL13_EXTEN ((uint32_t)0x002C0000) /* PLL input clock*13 */
  5064. #define RCC_PLLMULL14_EXTEN ((uint32_t)0x00300000) /* PLL input clock*14 */
  5065. #define RCC_PLLMULL6_5_EXTEN ((uint32_t)0x00340000) /* PLL input clock*6.5 */
  5066. #define RCC_PLLMULL15_EXTEN ((uint32_t)0x00380000) /* PLL input clock*15 */
  5067. #define RCC_PLLMULL16_EXTEN ((uint32_t)0x003C0000) /* PLL input clock*16 */
  5068. #define RCC_USBPRE ((uint32_t)0x00400000) /* USB Device prescaler */
  5069. #define RCC_CFGR0_MCO ((uint32_t)0x0F000000) /* MCO[3:0] bits (Microcontroller Clock Output) */
  5070. #define RCC_MCO_0 ((uint32_t)0x01000000) /* Bit 0 */
  5071. #define RCC_MCO_1 ((uint32_t)0x02000000) /* Bit 1 */
  5072. #define RCC_MCO_2 ((uint32_t)0x04000000) /* Bit 2 */
  5073. #define RCC_MCO_3 ((uint32_t)0x08000000) /* Bit 3 */
  5074. #define RCC_MCO_NOCLOCK ((uint32_t)0x00000000) /* No clock */
  5075. #define RCC_CFGR0_MCO_SYSCLK ((uint32_t)0x04000000) /* System clock selected as MCO source */
  5076. #define RCC_CFGR0_MCO_HSI ((uint32_t)0x05000000) /* HSI clock selected as MCO source */
  5077. #define RCC_CFGR0_MCO_HSE ((uint32_t)0x06000000) /* HSE clock selected as MCO source */
  5078. #define RCC_CFGR0_MCO_PLL ((uint32_t)0x07000000) /* PLL clock divided by 2 selected as MCO source */
  5079. #define RCC_CFGR0_MCO_PLL2 ((uint32_t)0x08000000)
  5080. #define RCC_CFGR0_MCO_PLL3D2 ((uint32_t)0x09000000) /* PLL3 clock divided by 2 selected as MCO source */
  5081. #define RCC_CFGR0_MCO_XT1 ((uint32_t)0x0A000000)
  5082. #define RCC_CFGR0_MCO_PLL3 ((uint32_t)0x0B000000)
  5083. #define RCC_CFGR0_ETHPRE ((uint32_t)0x10000000)
  5084. #define RCC_CFGR0_ADCDUTY ((uint32_t)0x80000000)
  5085. #define RCC_CFGR0_ADCDUTY_SEL ((uint32_t)0x40000000)
  5086. /******************* Bit definition for RCC_INTR register ********************/
  5087. #define RCC_LSIRDYF ((uint32_t)0x00000001) /* LSI Ready Interrupt flag */
  5088. #define RCC_LSERDYF ((uint32_t)0x00000002) /* LSE Ready Interrupt flag */
  5089. #define RCC_HSIRDYF ((uint32_t)0x00000004) /* HSI Ready Interrupt flag */
  5090. #define RCC_HSERDYF ((uint32_t)0x00000008) /* HSE Ready Interrupt flag */
  5091. #define RCC_PLLRDYF ((uint32_t)0x00000010) /* PLL Ready Interrupt flag */
  5092. #define RCC_PLL2RDYF ((uint32_t)0x00000020)
  5093. #define RCC_PLL3RDYF ((uint32_t)0x00000040)
  5094. #define RCC_CSSF ((uint32_t)0x00000080) /* Clock Security System Interrupt flag */
  5095. #define RCC_LSIRDYIE ((uint32_t)0x00000100) /* LSI Ready Interrupt Enable */
  5096. #define RCC_LSERDYIE ((uint32_t)0x00000200) /* LSE Ready Interrupt Enable */
  5097. #define RCC_HSIRDYIE ((uint32_t)0x00000400) /* HSI Ready Interrupt Enable */
  5098. #define RCC_HSERDYIE ((uint32_t)0x00000800) /* HSE Ready Interrupt Enable */
  5099. #define RCC_PLLRDYIE ((uint32_t)0x00001000) /* PLL Ready Interrupt Enable */
  5100. #define RCC_PLL2RDYIE ((uint32_t)0x00002000)
  5101. #define RCC_PLL3RDYIE ((uint32_t)0x00004000)
  5102. #define RCC_LSIRDYC ((uint32_t)0x00010000) /* LSI Ready Interrupt Clear */
  5103. #define RCC_LSERDYC ((uint32_t)0x00020000) /* LSE Ready Interrupt Clear */
  5104. #define RCC_HSIRDYC ((uint32_t)0x00040000) /* HSI Ready Interrupt Clear */
  5105. #define RCC_HSERDYC ((uint32_t)0x00080000) /* HSE Ready Interrupt Clear */
  5106. #define RCC_PLLRDYC ((uint32_t)0x00100000) /* PLL Ready Interrupt Clear */
  5107. #define RCC_PLL2RDYC ((uint32_t)0x00200000)
  5108. #define RCC_PLL3RDYC ((uint32_t)0x00400000)
  5109. #define RCC_CSSC ((uint32_t)0x00800000) /* Clock Security System Interrupt Clear */
  5110. /***************** Bit definition for RCC_APB2PRSTR register *****************/
  5111. #define RCC_AFIORST ((uint32_t)0x00000001) /* Alternate Function I/O reset */
  5112. #define RCC_IOPARST ((uint32_t)0x00000004) /* I/O port A reset */
  5113. #define RCC_IOPBRST ((uint32_t)0x00000008) /* I/O port B reset */
  5114. #define RCC_IOPCRST ((uint32_t)0x00000010) /* I/O port C reset */
  5115. #define RCC_IOPDRST ((uint32_t)0x00000020) /* I/O port D reset */
  5116. #define RCC_IOPERST ((uint32_t)0x00000040)
  5117. #define RCC_ADC1RST ((uint32_t)0x00000200) /* ADC 1 interface reset */
  5118. #define RCC_ADC2RST ((uint32_t)0x00000400) /* ADC 2 interface reset */
  5119. #define RCC_TIM1RST ((uint32_t)0x00000800) /* TIM1 Timer reset */
  5120. #define RCC_SPI1RST ((uint32_t)0x00001000) /* SPI 1 reset */
  5121. #define RCC_TIM8RST ((uint32_t)0x00002000)
  5122. #define RCC_USART1RST ((uint32_t)0x00004000) /* USART1 reset */
  5123. #define RCC_TIM9RST ((uint32_t)0x00080000)
  5124. #define RCC_TIM10RST ((uint32_t)0x00100000)
  5125. /***************** Bit definition for RCC_APB1PRSTR register *****************/
  5126. #define RCC_TIM2RST ((uint32_t)0x00000001) /* Timer 2 reset */
  5127. #define RCC_TIM3RST ((uint32_t)0x00000002) /* Timer 3 reset */
  5128. #define RCC_TIM4RST ((uint32_t)0x00000004) /* Timer 4 reset */
  5129. #define RCC_TIM5RST ((uint32_t)0x00000008) /* Timer 5 reset */
  5130. #define RCC_TIM6RST ((uint32_t)0x00000010) /* Timer 6 reset */
  5131. #define RCC_TIM7RST ((uint32_t)0x00000020) /* Timer 7 reset */
  5132. #define RCC_USART6RST ((uint32_t)0x00000040) /* USART 2 reset */
  5133. #define RCC_USART7RST ((uint32_t)0x00000080) /* USART 2 reset */
  5134. #define RCC_USART8RST ((uint32_t)0x00000100) /* USART 2 reset */
  5135. #define RCC_WWDGRST ((uint32_t)0x00000800) /* Window Watchdog reset */
  5136. #define RCC_SPI2RST ((uint32_t)0x00004000) /* SPI 2 reset */
  5137. #define RCC_SPI3RST ((uint32_t)0x00008000) /* SPI 3 reset */
  5138. #define RCC_USART2RST ((uint32_t)0x00020000) /* USART 2 reset */
  5139. #define RCC_USART3RST ((uint32_t)0x00040000) /* USART 3 reset */
  5140. #define RCC_USART4RST ((uint32_t)0x00080000) /* USART 4 reset */
  5141. #define RCC_USART5RST ((uint32_t)0x00100000) /* USART 5 reset */
  5142. #define RCC_I2C1RST ((uint32_t)0x00200000) /* I2C 1 reset */
  5143. #define RCC_I2C2RST ((uint32_t)0x00400000) /* I2C 2 reset */
  5144. #define RCC_USBRST ((uint32_t)0x00800000) /* USB Device reset */
  5145. #define RCC_CAN1RST ((uint32_t)0x02000000) /* CAN1 reset */
  5146. #define RCC_CAN2RST ((uint32_t)0x04000000) /* CAN2 reset */
  5147. #define RCC_BKPRST ((uint32_t)0x08000000) /* Backup interface reset */
  5148. #define RCC_PWRRST ((uint32_t)0x10000000) /* Power interface reset */
  5149. #define RCC_DACRST ((uint32_t)0x20000000) /* DAC reset */
  5150. /****************** Bit definition for RCC_AHBPCENR register ******************/
  5151. #define RCC_DMA1EN ((uint16_t)0x0001) /* DMA1 clock enable */
  5152. #define RCC_DMA2EN ((uint16_t)0x0002)
  5153. #define RCC_SRAMEN ((uint16_t)0x0004) /* SRAM interface clock enable */
  5154. #define RCC_CRCEN ((uint16_t)0x0040) /* CRC clock enable */
  5155. #define RCC_FSMCEN ((uint16_t)0x0100)
  5156. #define RCC_RNGEN ((uint16_t)0x0200)
  5157. #define RCC_SDIOEN ((uint16_t)0x0400)
  5158. #define RCC_USBHSEN ((uint16_t)0x0800)
  5159. #define RCC_OTGFSEN ((uint16_t)0x1000)
  5160. #define RCC_DVPEN ((uint16_t)0x2000)
  5161. #define RCC_ETHMACEN ((uint16_t)0x4000)
  5162. #define RCC_ETHMACTXEN ((uint16_t)0x8000)
  5163. #define RCC_ETHMACRXEN ((uint32_t)0x10000)
  5164. #define RCC_BLEC ((uint32_t)0x10000)
  5165. #define RCC_BLES ((uint32_t)0x20000)
  5166. /****************** Bit definition for RCC_APB2PCENR register *****************/
  5167. #define RCC_AFIOEN ((uint32_t)0x00000001) /* Alternate Function I/O clock enable */
  5168. #define RCC_IOPAEN ((uint32_t)0x00000004) /* I/O port A clock enable */
  5169. #define RCC_IOPBEN ((uint32_t)0x00000008) /* I/O port B clock enable */
  5170. #define RCC_IOPCEN ((uint32_t)0x00000010) /* I/O port C clock enable */
  5171. #define RCC_IOPDEN ((uint32_t)0x00000020) /* I/O port D clock enable */
  5172. #define RCC_IOPEEN ((uint32_t)0x00000040)
  5173. #define RCC_ADC1EN ((uint32_t)0x00000200) /* ADC 1 interface clock enable */
  5174. #define RCC_ADC2EN ((uint32_t)0x00000400) /* ADC 2 interface clock enable */
  5175. #define RCC_TIM1EN ((uint32_t)0x00000800) /* TIM1 Timer clock enable */
  5176. #define RCC_SPI1EN ((uint32_t)0x00001000) /* SPI 1 clock enable */
  5177. #define RCC_TIM8EN ((uint32_t)0x00002000)
  5178. #define RCC_USART1EN ((uint32_t)0x00004000) /* USART1 clock enable */
  5179. #define RCC_TIM9EN ((uint32_t)0x00080000)
  5180. #define RCC_TIM10EN ((uint32_t)0x00100000)
  5181. /***************** Bit definition for RCC_APB1PCENR register ******************/
  5182. #define RCC_TIM2EN ((uint32_t)0x00000001) /* Timer 2 clock enabled*/
  5183. #define RCC_TIM3EN ((uint32_t)0x00000002) /* Timer 3 clock enable */
  5184. #define RCC_TIM4EN ((uint32_t)0x00000004)
  5185. #define RCC_TIM5EN ((uint32_t)0x00000008)
  5186. #define RCC_TIM6EN ((uint32_t)0x00000010)
  5187. #define RCC_TIM7EN ((uint32_t)0x00000020)
  5188. #define RCC_USART6EN ((uint32_t)0x00000040)
  5189. #define RCC_USART7EN ((uint32_t)0x00000080)
  5190. #define RCC_USART8EN ((uint32_t)0x00000100)
  5191. #define RCC_WWDGEN ((uint32_t)0x00000800) /* Window Watchdog clock enable */
  5192. #define RCC_SPI2EN ((uint32_t)0x00004000)
  5193. #define RCC_SPI3EN ((uint32_t)0x00008000)
  5194. #define RCC_USART2EN ((uint32_t)0x00020000) /* USART 2 clock enable */
  5195. #define RCC_USART3EN ((uint32_t)0x00040000)
  5196. #define RCC_USART4EN ((uint32_t)0x00080000)
  5197. #define RCC_USART5EN ((uint32_t)0x00100000)
  5198. #define RCC_I2C1EN ((uint32_t)0x00200000) /* I2C 1 clock enable */
  5199. #define RCC_I2C2EN ((uint32_t)0x00400000)
  5200. #define RCC_USBEN ((uint32_t)0x00800000) /* USB Device clock enable */
  5201. #define RCC_CAN1EN ((uint32_t)0x02000000)
  5202. #define RCC_CAN2EN ((uint32_t)0x04000000)
  5203. #define RCC_BKPEN ((uint32_t)0x08000000) /* Backup interface clock enable */
  5204. #define RCC_PWREN ((uint32_t)0x10000000) /* Power interface clock enable */
  5205. #define RCC_DACEN ((uint32_t)0x20000000)
  5206. /******************* Bit definition for RCC_BDCTLR register *******************/
  5207. #define RCC_LSEON ((uint32_t)0x00000001) /* External Low Speed oscillator enable */
  5208. #define RCC_LSERDY ((uint32_t)0x00000002) /* External Low Speed oscillator Ready */
  5209. #define RCC_LSEBYP ((uint32_t)0x00000004) /* External Low Speed oscillator Bypass */
  5210. #define RCC_RTCSEL ((uint32_t)0x00000300) /* RTCSEL[1:0] bits (RTC clock source selection) */
  5211. #define RCC_RTCSEL_0 ((uint32_t)0x00000100) /* Bit 0 */
  5212. #define RCC_RTCSEL_1 ((uint32_t)0x00000200) /* Bit 1 */
  5213. #define RCC_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /* No clock */
  5214. #define RCC_RTCSEL_LSE ((uint32_t)0x00000100) /* LSE oscillator clock used as RTC clock */
  5215. #define RCC_RTCSEL_LSI ((uint32_t)0x00000200) /* LSI oscillator clock used as RTC clock */
  5216. #define RCC_RTCSEL_HSE ((uint32_t)0x00000300)
  5217. #define RCC_RTCEN ((uint32_t)0x00008000) /* RTC clock enable */
  5218. #define RCC_BDRST ((uint32_t)0x00010000) /* Backup domain software reset */
  5219. /******************* Bit definition for RCC_RSTSCKR register ********************/
  5220. #define RCC_LSION ((uint32_t)0x00000001) /* Internal Low Speed oscillator enable */
  5221. #define RCC_LSIRDY ((uint32_t)0x00000002) /* Internal Low Speed oscillator Ready */
  5222. #define RCC_RMVF ((uint32_t)0x01000000) /* Remove reset flag */
  5223. #define RCC_PINRSTF ((uint32_t)0x04000000) /* PIN reset flag */
  5224. #define RCC_PORRSTF ((uint32_t)0x08000000) /* POR/PDR reset flag */
  5225. #define RCC_SFTRSTF ((uint32_t)0x10000000) /* Software Reset flag */
  5226. #define RCC_IWDGRSTF ((uint32_t)0x20000000) /* Independent Watchdog reset flag */
  5227. #define RCC_WWDGRSTF ((uint32_t)0x40000000) /* Window watchdog reset flag */
  5228. #define RCC_LPWRRSTF ((uint32_t)0x80000000) /* Low-Power reset flag */
  5229. /******************* Bit definition for RCC_AHBRSTR register ********************/
  5230. #define RCC_OTGFSRST ((uint32_t)0x00001000)
  5231. #define RCC_DVPRST ((uint32_t)0x00002000)
  5232. #define RCC_ETHMACRST ((uint32_t)0x00004000)
  5233. /******************* Bit definition for RCC_CFGR2 register ********************/
  5234. #define RCC_PREDIV1 ((uint32_t)0x0000000F)
  5235. #define RCC_PREDIV1_0 ((uint32_t)0x00000001)
  5236. #define RCC_PREDIV1_1 ((uint32_t)0x00000002)
  5237. #define RCC_PREDIV1_2 ((uint32_t)0x00000004)
  5238. #define RCC_PREDIV1_3 ((uint32_t)0x00000008)
  5239. #define RCC_PREDIV2 ((uint32_t)0x000000F0)
  5240. #define RCC_PREDIV2_0 ((uint32_t)0x00000010)
  5241. #define RCC_PREDIV2_1 ((uint32_t)0x00000020)
  5242. #define RCC_PREDIV2_2 ((uint32_t)0x00000040)
  5243. #define RCC_PREDIV2_3 ((uint32_t)0x00000080)
  5244. #define RCC_PLL2MUL ((uint32_t)0x00000F00)
  5245. #define RCC_PLL2MUL_0 ((uint32_t)0x00000100)
  5246. #define RCC_PLL2MUL_1 ((uint32_t)0x00000200)
  5247. #define RCC_PLL2MUL_2 ((uint32_t)0x00000400)
  5248. #define RCC_PLL2MUL_3 ((uint32_t)0x00000800)
  5249. #define RCC_PLL3MUL ((uint32_t)0x0000F000)
  5250. #define RCC_PLL3MUL_0 ((uint32_t)0x00001000)
  5251. #define RCC_PLL3MUL_1 ((uint32_t)0x00002000)
  5252. #define RCC_PLL3MUL_2 ((uint32_t)0x00004000)
  5253. #define RCC_PLL3MUL_3 ((uint32_t)0x00008000)
  5254. #define RCC_PREDIV1SRC ((uint32_t)0x00010000)
  5255. #define RCC_I2S2SRC ((uint32_t)0x00020000)
  5256. #define RCC_I2S3SRC ((uint32_t)0x00040000)
  5257. #define RCC_RNGSRC ((uint32_t)0x00080000)
  5258. #define RCC_ETH1GSRC ((uint32_t)0x00300000)
  5259. #define RCC_ETH1GSRC_0 ((uint32_t)0x00100000)
  5260. #define RCC_ETH1GSRC_1 ((uint32_t)0x00200000)
  5261. #define RCC_ETH1GEN ((uint32_t)0x00400000)
  5262. #define RCC_USBHSDIV ((uint32_t)0x07000000)
  5263. #define RCC_USBHSDIV_0 ((uint32_t)0x01000000)
  5264. #define RCC_USBHSDIV_1 ((uint32_t)0x02000000)
  5265. #define RCC_USBHSDIV_2 ((uint32_t)0x04000000)
  5266. #define RCC_USBHSPLLSRC ((uint32_t)0x08000000)
  5267. #define RCC_USBHSCLK ((uint32_t)0x30000000)
  5268. #define RCC_USBHSCLK_0 ((uint32_t)0x10000000)
  5269. #define RCC_USBHSCLK_1 ((uint32_t)0x20000000)
  5270. #define RCC_USBHSPLL ((uint32_t)0x40000000)
  5271. #define RCC_USBFSSRC ((uint32_t)0x80000000)
  5272. /******************* Bit definition for RCC_HSE_CAL_CTRL register ********************/
  5273. #define RCC_HSEITRIM ((uint32_t)0x01000000)
  5274. #define RCC_HSEFAULT ((uint32_t)0x08000000)
  5275. #define RCC_HSEC ((uint32_t)0x70000000)
  5276. #define RCC_HSEC_0 ((uint32_t)0x10000000)
  5277. #define RCC_HSEC_1 ((uint32_t)0x20000000)
  5278. #define RCC_HSEC_2 ((uint32_t)0x40000000)
  5279. /******************* Bit definition for RCC_LSI32K_TUNE register ********************/
  5280. #define RCC_HTUNE ((uint16_t)0x1000)
  5281. #define RCC_LTUNE ((uint16_t)0x0011)
  5282. /******************* Bit definition for RCC_LSI32K_CAL_CFG register ********************/
  5283. #define RCC_CNTVLU ((uint8_t)0x0F)
  5284. #define RCC_CNTVLU_0 ((uint8_t)0x01)
  5285. #define RCC_CNTVLU_1 ((uint8_t)0x02)
  5286. #define RCC_CNTVLU_2 ((uint8_t)0x04)
  5287. #define RCC_CNTVLU_3 ((uint8_t)0x08)
  5288. #define RCC_HALTMD ((uint8_t)0x10)
  5289. #define RCC_WKUPEN ((uint8_t)0x20)
  5290. #define RCC_LPEN ((uint8_t)0x40)
  5291. /******************* Bit definition for RCC_LSI32K_CAL_STATR register ********************/
  5292. #define RCC_CNTOV ((uint16_t)0x4000)
  5293. #define RCC_IFEND ((uint16_t)0x8000)
  5294. /******************* Bit definition for RCC_LSI32K_CAL_CTRL register ********************/
  5295. #define RCC_CALINTEN ((uint8_t)0x01)
  5296. #define RCC_CALEN ((uint8_t)0x02)
  5297. #define RCC_HALT ((uint8_t)0x80)
  5298. /******************************************************************************/
  5299. /* RNG */
  5300. /******************************************************************************/
  5301. /******************** Bit definition for RNG_CR register *******************/
  5302. #define RNG_CR_RNGEN ((uint32_t)0x00000004)
  5303. #define RNG_CR_IE ((uint32_t)0x00000008)
  5304. /******************** Bit definition for RNG_SR register *******************/
  5305. #define RNG_SR_DRDY ((uint32_t)0x00000001)
  5306. #define RNG_SR_CECS ((uint32_t)0x00000002)
  5307. #define RNG_SR_SECS ((uint32_t)0x00000004)
  5308. #define RNG_SR_CEIS ((uint32_t)0x00000020)
  5309. #define RNG_SR_SEIS ((uint32_t)0x00000040)
  5310. /******************************************************************************/
  5311. /* Real-Time Clock */
  5312. /******************************************************************************/
  5313. /******************* Bit definition for RTC_CTLRH register ********************/
  5314. #define RTC_CTLRH_SECIE ((uint8_t)0x01) /* Second Interrupt Enable */
  5315. #define RTC_CTLRH_ALRIE ((uint8_t)0x02) /* Alarm Interrupt Enable */
  5316. #define RTC_CTLRH_OWIE ((uint8_t)0x04) /* OverfloW Interrupt Enable */
  5317. /******************* Bit definition for RTC_CTLRL register ********************/
  5318. #define RTC_CTLRL_SECF ((uint8_t)0x01) /* Second Flag */
  5319. #define RTC_CTLRL_ALRF ((uint8_t)0x02) /* Alarm Flag */
  5320. #define RTC_CTLRL_OWF ((uint8_t)0x04) /* OverfloW Flag */
  5321. #define RTC_CTLRL_RSF ((uint8_t)0x08) /* Registers Synchronized Flag */
  5322. #define RTC_CTLRL_CNF ((uint8_t)0x10) /* Configuration Flag */
  5323. #define RTC_CTLRL_RTOFF ((uint8_t)0x20) /* RTC operation OFF */
  5324. /******************* Bit definition for RTC_PSCH register *******************/
  5325. #define RTC_PSCH_PRL ((uint16_t)0x000F) /* RTC Prescaler Reload Value High */
  5326. /******************* Bit definition for RTC_PRLL register *******************/
  5327. #define RTC_PSCL_PRL ((uint16_t)0xFFFF) /* RTC Prescaler Reload Value Low */
  5328. /******************* Bit definition for RTC_DIVH register *******************/
  5329. #define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /* RTC Clock Divider High */
  5330. /******************* Bit definition for RTC_DIVL register *******************/
  5331. #define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /* RTC Clock Divider Low */
  5332. /******************* Bit definition for RTC_CNTH register *******************/
  5333. #define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /* RTC Counter High */
  5334. /******************* Bit definition for RTC_CNTL register *******************/
  5335. #define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /* RTC Counter Low */
  5336. /******************* Bit definition for RTC_ALRMH register *******************/
  5337. #define RTC_ALRMH_RTC_ALRM ((uint16_t)0xFFFF) /* RTC Alarm High */
  5338. /******************* Bit definition for RTC_ALRML register *******************/
  5339. #define RTC_ALRML_RTC_ALRM ((uint16_t)0xFFFF) /* RTC Alarm Low */
  5340. /******************************************************************************/
  5341. /* Serial Peripheral Interface */
  5342. /******************************************************************************/
  5343. /******************* Bit definition for SPI_CTLR1 register ********************/
  5344. #define SPI_CTLR1_CPHA ((uint16_t)0x0001) /* Clock Phase */
  5345. #define SPI_CTLR1_CPOL ((uint16_t)0x0002) /* Clock Polarity */
  5346. #define SPI_CTLR1_MSTR ((uint16_t)0x0004) /* Master Selection */
  5347. #define SPI_CTLR1_BR ((uint16_t)0x0038) /* BR[2:0] bits (Baud Rate Control) */
  5348. #define SPI_CTLR1_BR_0 ((uint16_t)0x0008) /* Bit 0 */
  5349. #define SPI_CTLR1_BR_1 ((uint16_t)0x0010) /* Bit 1 */
  5350. #define SPI_CTLR1_BR_2 ((uint16_t)0x0020) /* Bit 2 */
  5351. #define SPI_CTLR1_SPE ((uint16_t)0x0040) /* SPI Enable */
  5352. #define SPI_CTLR1_LSBFIRST ((uint16_t)0x0080) /* Frame Format */
  5353. #define SPI_CTLR1_SSI ((uint16_t)0x0100) /* Internal slave select */
  5354. #define SPI_CTLR1_SSM ((uint16_t)0x0200) /* Software slave management */
  5355. #define SPI_CTLR1_RXONLY ((uint16_t)0x0400) /* Receive only */
  5356. #define SPI_CTLR1_DFF ((uint16_t)0x0800) /* Data Frame Format */
  5357. #define SPI_CTLR1_CRCNEXT ((uint16_t)0x1000) /* Transmit CRC next */
  5358. #define SPI_CTLR1_CRCEN ((uint16_t)0x2000) /* Hardware CRC calculation enable */
  5359. #define SPI_CTLR1_BIDIOE ((uint16_t)0x4000) /* Output enable in bidirectional mode */
  5360. #define SPI_CTLR1_BIDIMODE ((uint16_t)0x8000) /* Bidirectional data mode enable */
  5361. /******************* Bit definition for SPI_CTLR2 register ********************/
  5362. #define SPI_CTLR2_RXDMAEN ((uint8_t)0x01) /* Rx Buffer DMA Enable */
  5363. #define SPI_CTLR2_TXDMAEN ((uint8_t)0x02) /* Tx Buffer DMA Enable */
  5364. #define SPI_CTLR2_SSOE ((uint8_t)0x04) /* SS Output Enable */
  5365. #define SPI_CTLR2_ERRIE ((uint8_t)0x20) /* Error Interrupt Enable */
  5366. #define SPI_CTLR2_RXNEIE ((uint8_t)0x40) /* RX buffer Not Empty Interrupt Enable */
  5367. #define SPI_CTLR2_TXEIE ((uint8_t)0x80) /* Tx buffer Empty Interrupt Enable */
  5368. /******************** Bit definition for SPI_STATR register ********************/
  5369. #define SPI_STATR_RXNE ((uint8_t)0x01) /* Receive buffer Not Empty */
  5370. #define SPI_STATR_TXE ((uint8_t)0x02) /* Transmit buffer Empty */
  5371. #define SPI_STATR_CHSIDE ((uint8_t)0x04) /* Channel side */
  5372. #define SPI_STATR_UDR ((uint8_t)0x08) /* Underrun flag */
  5373. #define SPI_STATR_CRCERR ((uint8_t)0x10) /* CRC Error flag */
  5374. #define SPI_STATR_MODF ((uint8_t)0x20) /* Mode fault */
  5375. #define SPI_STATR_OVR ((uint8_t)0x40) /* Overrun flag */
  5376. #define SPI_STATR_BSY ((uint8_t)0x80) /* Busy flag */
  5377. /******************** Bit definition for SPI_DATAR register ********************/
  5378. #define SPI_DATAR_DR ((uint16_t)0xFFFF) /* Data Register */
  5379. /******************* Bit definition for SPI_CRCR register ******************/
  5380. #define SPI_CRCR_CRCPOLY ((uint16_t)0xFFFF) /* CRC polynomial register */
  5381. /****************** Bit definition for SPI_RCRCR register ******************/
  5382. #define SPI_RCRCR_RXCRC ((uint16_t)0xFFFF) /* Rx CRC Register */
  5383. /****************** Bit definition for SPI_TCRCR register ******************/
  5384. #define SPI_TCRCR_TXCRC ((uint16_t)0xFFFF) /* Tx CRC Register */
  5385. /****************** Bit definition for SPI_I2SCFGR register *****************/
  5386. #define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /* Channel length (number of bits per audio channel) */
  5387. #define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /* DATLEN[1:0] bits (Data length to be transferred) */
  5388. #define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /* Bit 0 */
  5389. #define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /* Bit 1 */
  5390. #define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /* steady state clock polarity */
  5391. #define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /* I2SSTD[1:0] bits (I2S standard selection) */
  5392. #define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /* Bit 0 */
  5393. #define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /* Bit 1 */
  5394. #define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /* PCM frame synchronization */
  5395. #define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /* I2SCFG[1:0] bits (I2S configuration mode) */
  5396. #define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /* Bit 0 */
  5397. #define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /* Bit 1 */
  5398. #define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /* I2S Enable */
  5399. #define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /* I2S mode selection */
  5400. /****************** Bit definition for SPI_I2SPR register *******************/
  5401. #define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /* I2S Linear prescaler */
  5402. #define SPI_I2SPR_ODD ((uint16_t)0x0100) /* Odd factor for the prescaler */
  5403. #define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /* Master Clock Output Enable */
  5404. /****************** Bit definition for SPI_HSCR register *******************/
  5405. #define SPI_HSCR_HSRXEN ((uint16_t)0x0001)
  5406. #define SPI_HSCR_HSRXEN2 ((uint16_t)0x0004)
  5407. /******************************************************************************/
  5408. /* TIM */
  5409. /******************************************************************************/
  5410. /******************* Bit definition for TIM_CTLR1 register ********************/
  5411. #define TIM_CEN ((uint16_t)0x0001) /* Counter enable */
  5412. #define TIM_UDIS ((uint16_t)0x0002) /* Update disable */
  5413. #define TIM_URS ((uint16_t)0x0004) /* Update request source */
  5414. #define TIM_OPM ((uint16_t)0x0008) /* One pulse mode */
  5415. #define TIM_DIR ((uint16_t)0x0010) /* Direction */
  5416. #define TIM_CMS ((uint16_t)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */
  5417. #define TIM_CMS_0 ((uint16_t)0x0020) /* Bit 0 */
  5418. #define TIM_CMS_1 ((uint16_t)0x0040) /* Bit 1 */
  5419. #define TIM_ARPE ((uint16_t)0x0080) /* Auto-reload preload enable */
  5420. #define TIM_CTLR1_CKD ((uint16_t)0x0300) /* CKD[1:0] bits (clock division) */
  5421. #define TIM_CKD_0 ((uint16_t)0x0100) /* Bit 0 */
  5422. #define TIM_CKD_1 ((uint16_t)0x0200) /* Bit 1 */
  5423. /******************* Bit definition for TIM_CTLR2 register ********************/
  5424. #define TIM_CCPC ((uint16_t)0x0001) /* Capture/Compare Preloaded Control */
  5425. #define TIM_CCUS ((uint16_t)0x0004) /* Capture/Compare Control Update Selection */
  5426. #define TIM_CCDS ((uint16_t)0x0008) /* Capture/Compare DMA Selection */
  5427. #define TIM_MMS ((uint16_t)0x0070) /* MMS[2:0] bits (Master Mode Selection) */
  5428. #define TIM_MMS_0 ((uint16_t)0x0010) /* Bit 0 */
  5429. #define TIM_MMS_1 ((uint16_t)0x0020) /* Bit 1 */
  5430. #define TIM_MMS_2 ((uint16_t)0x0040) /* Bit 2 */
  5431. #define TIM_TI1S ((uint16_t)0x0080) /* TI1 Selection */
  5432. #define TIM_OIS1 ((uint16_t)0x0100) /* Output Idle state 1 (OC1 output) */
  5433. #define TIM_OIS1N ((uint16_t)0x0200) /* Output Idle state 1 (OC1N output) */
  5434. #define TIM_OIS2 ((uint16_t)0x0400) /* Output Idle state 2 (OC2 output) */
  5435. #define TIM_OIS2N ((uint16_t)0x0800) /* Output Idle state 2 (OC2N output) */
  5436. #define TIM_OIS3 ((uint16_t)0x1000) /* Output Idle state 3 (OC3 output) */
  5437. #define TIM_OIS3N ((uint16_t)0x2000) /* Output Idle state 3 (OC3N output) */
  5438. #define TIM_OIS4 ((uint16_t)0x4000) /* Output Idle state 4 (OC4 output) */
  5439. /******************* Bit definition for TIM_SMCFGR register *******************/
  5440. #define TIM_SMS ((uint16_t)0x0007) /* SMS[2:0] bits (Slave mode selection) */
  5441. #define TIM_SMS_0 ((uint16_t)0x0001) /* Bit 0 */
  5442. #define TIM_SMS_1 ((uint16_t)0x0002) /* Bit 1 */
  5443. #define TIM_SMS_2 ((uint16_t)0x0004) /* Bit 2 */
  5444. #define TIM_TS ((uint16_t)0x0070) /* TS[2:0] bits (Trigger selection) */
  5445. #define TIM_TS_0 ((uint16_t)0x0010) /* Bit 0 */
  5446. #define TIM_TS_1 ((uint16_t)0x0020) /* Bit 1 */
  5447. #define TIM_TS_2 ((uint16_t)0x0040) /* Bit 2 */
  5448. #define TIM_MSM ((uint16_t)0x0080) /* Master/slave mode */
  5449. #define TIM_ETF ((uint16_t)0x0F00) /* ETF[3:0] bits (External trigger filter) */
  5450. #define TIM_ETF_0 ((uint16_t)0x0100) /* Bit 0 */
  5451. #define TIM_ETF_1 ((uint16_t)0x0200) /* Bit 1 */
  5452. #define TIM_ETF_2 ((uint16_t)0x0400) /* Bit 2 */
  5453. #define TIM_ETF_3 ((uint16_t)0x0800) /* Bit 3 */
  5454. #define TIM_ETPS ((uint16_t)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */
  5455. #define TIM_ETPS_0 ((uint16_t)0x1000) /* Bit 0 */
  5456. #define TIM_ETPS_1 ((uint16_t)0x2000) /* Bit 1 */
  5457. #define TIM_ECE ((uint16_t)0x4000) /* External clock enable */
  5458. #define TIM_ETP ((uint16_t)0x8000) /* External trigger polarity */
  5459. /******************* Bit definition for TIM_DMAINTENR register *******************/
  5460. #define TIM_UIE ((uint16_t)0x0001) /* Update interrupt enable */
  5461. #define TIM_CC1IE ((uint16_t)0x0002) /* Capture/Compare 1 interrupt enable */
  5462. #define TIM_CC2IE ((uint16_t)0x0004) /* Capture/Compare 2 interrupt enable */
  5463. #define TIM_CC3IE ((uint16_t)0x0008) /* Capture/Compare 3 interrupt enable */
  5464. #define TIM_CC4IE ((uint16_t)0x0010) /* Capture/Compare 4 interrupt enable */
  5465. #define TIM_COMIE ((uint16_t)0x0020) /* COM interrupt enable */
  5466. #define TIM_TIE ((uint16_t)0x0040) /* Trigger interrupt enable */
  5467. #define TIM_BIE ((uint16_t)0x0080) /* Break interrupt enable */
  5468. #define TIM_UDE ((uint16_t)0x0100) /* Update DMA request enable */
  5469. #define TIM_CC1DE ((uint16_t)0x0200) /* Capture/Compare 1 DMA request enable */
  5470. #define TIM_CC2DE ((uint16_t)0x0400) /* Capture/Compare 2 DMA request enable */
  5471. #define TIM_CC3DE ((uint16_t)0x0800) /* Capture/Compare 3 DMA request enable */
  5472. #define TIM_CC4DE ((uint16_t)0x1000) /* Capture/Compare 4 DMA request enable */
  5473. #define TIM_COMDE ((uint16_t)0x2000) /* COM DMA request enable */
  5474. #define TIM_TDE ((uint16_t)0x4000) /* Trigger DMA request enable */
  5475. /******************** Bit definition for TIM_INTFR register ********************/
  5476. #define TIM_UIF ((uint16_t)0x0001) /* Update interrupt Flag */
  5477. #define TIM_CC1IF ((uint16_t)0x0002) /* Capture/Compare 1 interrupt Flag */
  5478. #define TIM_CC2IF ((uint16_t)0x0004) /* Capture/Compare 2 interrupt Flag */
  5479. #define TIM_CC3IF ((uint16_t)0x0008) /* Capture/Compare 3 interrupt Flag */
  5480. #define TIM_CC4IF ((uint16_t)0x0010) /* Capture/Compare 4 interrupt Flag */
  5481. #define TIM_COMIF ((uint16_t)0x0020) /* COM interrupt Flag */
  5482. #define TIM_TIF ((uint16_t)0x0040) /* Trigger interrupt Flag */
  5483. #define TIM_BIF ((uint16_t)0x0080) /* Break interrupt Flag */
  5484. #define TIM_CC1OF ((uint16_t)0x0200) /* Capture/Compare 1 Overcapture Flag */
  5485. #define TIM_CC2OF ((uint16_t)0x0400) /* Capture/Compare 2 Overcapture Flag */
  5486. #define TIM_CC3OF ((uint16_t)0x0800) /* Capture/Compare 3 Overcapture Flag */
  5487. #define TIM_CC4OF ((uint16_t)0x1000) /* Capture/Compare 4 Overcapture Flag */
  5488. /******************* Bit definition for TIM_SWEVGR register ********************/
  5489. #define TIM_UG ((uint8_t)0x01) /* Update Generation */
  5490. #define TIM_CC1G ((uint8_t)0x02) /* Capture/Compare 1 Generation */
  5491. #define TIM_CC2G ((uint8_t)0x04) /* Capture/Compare 2 Generation */
  5492. #define TIM_CC3G ((uint8_t)0x08) /* Capture/Compare 3 Generation */
  5493. #define TIM_CC4G ((uint8_t)0x10) /* Capture/Compare 4 Generation */
  5494. #define TIM_COMG ((uint8_t)0x20) /* Capture/Compare Control Update Generation */
  5495. #define TIM_TG ((uint8_t)0x40) /* Trigger Generation */
  5496. #define TIM_BG ((uint8_t)0x80) /* Break Generation */
  5497. /****************** Bit definition for TIM_CHCTLR1 register *******************/
  5498. #define TIM_CC1S ((uint16_t)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */
  5499. #define TIM_CC1S_0 ((uint16_t)0x0001) /* Bit 0 */
  5500. #define TIM_CC1S_1 ((uint16_t)0x0002) /* Bit 1 */
  5501. #define TIM_OC1FE ((uint16_t)0x0004) /* Output Compare 1 Fast enable */
  5502. #define TIM_OC1PE ((uint16_t)0x0008) /* Output Compare 1 Preload enable */
  5503. #define TIM_OC1M ((uint16_t)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */
  5504. #define TIM_OC1M_0 ((uint16_t)0x0010) /* Bit 0 */
  5505. #define TIM_OC1M_1 ((uint16_t)0x0020) /* Bit 1 */
  5506. #define TIM_OC1M_2 ((uint16_t)0x0040) /* Bit 2 */
  5507. #define TIM_OC1CE ((uint16_t)0x0080) /* Output Compare 1Clear Enable */
  5508. #define TIM_CC2S ((uint16_t)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */
  5509. #define TIM_CC2S_0 ((uint16_t)0x0100) /* Bit 0 */
  5510. #define TIM_CC2S_1 ((uint16_t)0x0200) /* Bit 1 */
  5511. #define TIM_OC2FE ((uint16_t)0x0400) /* Output Compare 2 Fast enable */
  5512. #define TIM_OC2PE ((uint16_t)0x0800) /* Output Compare 2 Preload enable */
  5513. #define TIM_OC2M ((uint16_t)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */
  5514. #define TIM_OC2M_0 ((uint16_t)0x1000) /* Bit 0 */
  5515. #define TIM_OC2M_1 ((uint16_t)0x2000) /* Bit 1 */
  5516. #define TIM_OC2M_2 ((uint16_t)0x4000) /* Bit 2 */
  5517. #define TIM_OC2CE ((uint16_t)0x8000) /* Output Compare 2 Clear Enable */
  5518. #define TIM_IC1PSC ((uint16_t)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
  5519. #define TIM_IC1PSC_0 ((uint16_t)0x0004) /* Bit 0 */
  5520. #define TIM_IC1PSC_1 ((uint16_t)0x0008) /* Bit 1 */
  5521. #define TIM_IC1F ((uint16_t)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */
  5522. #define TIM_IC1F_0 ((uint16_t)0x0010) /* Bit 0 */
  5523. #define TIM_IC1F_1 ((uint16_t)0x0020) /* Bit 1 */
  5524. #define TIM_IC1F_2 ((uint16_t)0x0040) /* Bit 2 */
  5525. #define TIM_IC1F_3 ((uint16_t)0x0080) /* Bit 3 */
  5526. #define TIM_IC2PSC ((uint16_t)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
  5527. #define TIM_IC2PSC_0 ((uint16_t)0x0400) /* Bit 0 */
  5528. #define TIM_IC2PSC_1 ((uint16_t)0x0800) /* Bit 1 */
  5529. #define TIM_IC2F ((uint16_t)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */
  5530. #define TIM_IC2F_0 ((uint16_t)0x1000) /* Bit 0 */
  5531. #define TIM_IC2F_1 ((uint16_t)0x2000) /* Bit 1 */
  5532. #define TIM_IC2F_2 ((uint16_t)0x4000) /* Bit 2 */
  5533. #define TIM_IC2F_3 ((uint16_t)0x8000) /* Bit 3 */
  5534. /****************** Bit definition for TIM_CHCTLR2 register *******************/
  5535. #define TIM_CC3S ((uint16_t)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */
  5536. #define TIM_CC3S_0 ((uint16_t)0x0001) /* Bit 0 */
  5537. #define TIM_CC3S_1 ((uint16_t)0x0002) /* Bit 1 */
  5538. #define TIM_OC3FE ((uint16_t)0x0004) /* Output Compare 3 Fast enable */
  5539. #define TIM_OC3PE ((uint16_t)0x0008) /* Output Compare 3 Preload enable */
  5540. #define TIM_OC3M ((uint16_t)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */
  5541. #define TIM_OC3M_0 ((uint16_t)0x0010) /* Bit 0 */
  5542. #define TIM_OC3M_1 ((uint16_t)0x0020) /* Bit 1 */
  5543. #define TIM_OC3M_2 ((uint16_t)0x0040) /* Bit 2 */
  5544. #define TIM_OC3CE ((uint16_t)0x0080) /* Output Compare 3 Clear Enable */
  5545. #define TIM_CC4S ((uint16_t)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */
  5546. #define TIM_CC4S_0 ((uint16_t)0x0100) /* Bit 0 */
  5547. #define TIM_CC4S_1 ((uint16_t)0x0200) /* Bit 1 */
  5548. #define TIM_OC4FE ((uint16_t)0x0400) /* Output Compare 4 Fast enable */
  5549. #define TIM_OC4PE ((uint16_t)0x0800) /* Output Compare 4 Preload enable */
  5550. #define TIM_OC4M ((uint16_t)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */
  5551. #define TIM_OC4M_0 ((uint16_t)0x1000) /* Bit 0 */
  5552. #define TIM_OC4M_1 ((uint16_t)0x2000) /* Bit 1 */
  5553. #define TIM_OC4M_2 ((uint16_t)0x4000) /* Bit 2 */
  5554. #define TIM_OC4CE ((uint16_t)0x8000) /* Output Compare 4 Clear Enable */
  5555. #define TIM_IC3PSC ((uint16_t)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
  5556. #define TIM_IC3PSC_0 ((uint16_t)0x0004) /* Bit 0 */
  5557. #define TIM_IC3PSC_1 ((uint16_t)0x0008) /* Bit 1 */
  5558. #define TIM_IC3F ((uint16_t)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */
  5559. #define TIM_IC3F_0 ((uint16_t)0x0010) /* Bit 0 */
  5560. #define TIM_IC3F_1 ((uint16_t)0x0020) /* Bit 1 */
  5561. #define TIM_IC3F_2 ((uint16_t)0x0040) /* Bit 2 */
  5562. #define TIM_IC3F_3 ((uint16_t)0x0080) /* Bit 3 */
  5563. #define TIM_IC4PSC ((uint16_t)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
  5564. #define TIM_IC4PSC_0 ((uint16_t)0x0400) /* Bit 0 */
  5565. #define TIM_IC4PSC_1 ((uint16_t)0x0800) /* Bit 1 */
  5566. #define TIM_IC4F ((uint16_t)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */
  5567. #define TIM_IC4F_0 ((uint16_t)0x1000) /* Bit 0 */
  5568. #define TIM_IC4F_1 ((uint16_t)0x2000) /* Bit 1 */
  5569. #define TIM_IC4F_2 ((uint16_t)0x4000) /* Bit 2 */
  5570. #define TIM_IC4F_3 ((uint16_t)0x8000) /* Bit 3 */
  5571. /******************* Bit definition for TIM_CCER register *******************/
  5572. #define TIM_CC1E ((uint16_t)0x0001) /* Capture/Compare 1 output enable */
  5573. #define TIM_CC1P ((uint16_t)0x0002) /* Capture/Compare 1 output Polarity */
  5574. #define TIM_CC1NE ((uint16_t)0x0004) /* Capture/Compare 1 Complementary output enable */
  5575. #define TIM_CC1NP ((uint16_t)0x0008) /* Capture/Compare 1 Complementary output Polarity */
  5576. #define TIM_CC2E ((uint16_t)0x0010) /* Capture/Compare 2 output enable */
  5577. #define TIM_CC2P ((uint16_t)0x0020) /* Capture/Compare 2 output Polarity */
  5578. #define TIM_CC2NE ((uint16_t)0x0040) /* Capture/Compare 2 Complementary output enable */
  5579. #define TIM_CC2NP ((uint16_t)0x0080) /* Capture/Compare 2 Complementary output Polarity */
  5580. #define TIM_CC3E ((uint16_t)0x0100) /* Capture/Compare 3 output enable */
  5581. #define TIM_CC3P ((uint16_t)0x0200) /* Capture/Compare 3 output Polarity */
  5582. #define TIM_CC3NE ((uint16_t)0x0400) /* Capture/Compare 3 Complementary output enable */
  5583. #define TIM_CC3NP ((uint16_t)0x0800) /* Capture/Compare 3 Complementary output Polarity */
  5584. #define TIM_CC4E ((uint16_t)0x1000) /* Capture/Compare 4 output enable */
  5585. #define TIM_CC4P ((uint16_t)0x2000) /* Capture/Compare 4 output Polarity */
  5586. /******************* Bit definition for TIM_CNT register ********************/
  5587. #define TIM_CNT ((uint16_t)0xFFFF) /* Counter Value */
  5588. /******************* Bit definition for TIM_PSC register ********************/
  5589. #define TIM_PSC ((uint16_t)0xFFFF) /* Prescaler Value */
  5590. /******************* Bit definition for TIM_ATRLR register ********************/
  5591. #define TIM_ARR ((uint16_t)0xFFFF) /* actual auto-reload Value */
  5592. /******************* Bit definition for TIM_RPTCR register ********************/
  5593. #define TIM_REP ((uint8_t)0xFF) /* Repetition Counter Value */
  5594. /******************* Bit definition for TIM_CH1CVR register *******************/
  5595. #define TIM_CCR1 ((uint16_t)0xFFFF) /* Capture/Compare 1 Value */
  5596. /******************* Bit definition for TIM_CH2CVR register *******************/
  5597. #define TIM_CCR2 ((uint16_t)0xFFFF) /* Capture/Compare 2 Value */
  5598. /******************* Bit definition for TIM_CH3CVR register *******************/
  5599. #define TIM_CCR3 ((uint16_t)0xFFFF) /* Capture/Compare 3 Value */
  5600. /******************* Bit definition for TIM_CH4CVR register *******************/
  5601. #define TIM_CCR4 ((uint16_t)0xFFFF) /* Capture/Compare 4 Value */
  5602. /******************* Bit definition for TIM_BDTR register *******************/
  5603. #define TIM_DTG ((uint16_t)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */
  5604. #define TIM_DTG_0 ((uint16_t)0x0001) /* Bit 0 */
  5605. #define TIM_DTG_1 ((uint16_t)0x0002) /* Bit 1 */
  5606. #define TIM_DTG_2 ((uint16_t)0x0004) /* Bit 2 */
  5607. #define TIM_DTG_3 ((uint16_t)0x0008) /* Bit 3 */
  5608. #define TIM_DTG_4 ((uint16_t)0x0010) /* Bit 4 */
  5609. #define TIM_DTG_5 ((uint16_t)0x0020) /* Bit 5 */
  5610. #define TIM_DTG_6 ((uint16_t)0x0040) /* Bit 6 */
  5611. #define TIM_DTG_7 ((uint16_t)0x0080) /* Bit 7 */
  5612. #define TIM_LOCK ((uint16_t)0x0300) /* LOCK[1:0] bits (Lock Configuration) */
  5613. #define TIM_LOCK_0 ((uint16_t)0x0100) /* Bit 0 */
  5614. #define TIM_LOCK_1 ((uint16_t)0x0200) /* Bit 1 */
  5615. #define TIM_OSSI ((uint16_t)0x0400) /* Off-State Selection for Idle mode */
  5616. #define TIM_OSSR ((uint16_t)0x0800) /* Off-State Selection for Run mode */
  5617. #define TIM_BKE ((uint16_t)0x1000) /* Break enable */
  5618. #define TIM_BKP ((uint16_t)0x2000) /* Break Polarity */
  5619. #define TIM_AOE ((uint16_t)0x4000) /* Automatic Output enable */
  5620. #define TIM_MOE ((uint16_t)0x8000) /* Main Output enable */
  5621. /******************* Bit definition for TIM_DMACFGR register ********************/
  5622. #define TIM_DBA ((uint16_t)0x001F) /* DBA[4:0] bits (DMA Base Address) */
  5623. #define TIM_DBA_0 ((uint16_t)0x0001) /* Bit 0 */
  5624. #define TIM_DBA_1 ((uint16_t)0x0002) /* Bit 1 */
  5625. #define TIM_DBA_2 ((uint16_t)0x0004) /* Bit 2 */
  5626. #define TIM_DBA_3 ((uint16_t)0x0008) /* Bit 3 */
  5627. #define TIM_DBA_4 ((uint16_t)0x0010) /* Bit 4 */
  5628. #define TIM_DBL ((uint16_t)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */
  5629. #define TIM_DBL_0 ((uint16_t)0x0100) /* Bit 0 */
  5630. #define TIM_DBL_1 ((uint16_t)0x0200) /* Bit 1 */
  5631. #define TIM_DBL_2 ((uint16_t)0x0400) /* Bit 2 */
  5632. #define TIM_DBL_3 ((uint16_t)0x0800) /* Bit 3 */
  5633. #define TIM_DBL_4 ((uint16_t)0x1000) /* Bit 4 */
  5634. /******************* Bit definition for TIM_DMAADR register *******************/
  5635. #define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /* DMA register for burst accesses */
  5636. /******************* Bit definition for TIM_AUX register *******************/
  5637. #define TIM_AUX_CAPCH2_ED ((uint16_t)0x0001)
  5638. #define TIM_AUX_CAPCH3_ED ((uint16_t)0x0002)
  5639. #define TIM_AUX_CAPCH4_ED ((uint16_t)0x0004)
  5640. /******************************************************************************/
  5641. /* Universal Synchronous Asynchronous Receiver Transmitter */
  5642. /******************************************************************************/
  5643. /******************* Bit definition for USART_STATR register *******************/
  5644. #define USART_STATR_PE ((uint16_t)0x0001) /* Parity Error */
  5645. #define USART_STATR_FE ((uint16_t)0x0002) /* Framing Error */
  5646. #define USART_STATR_NE ((uint16_t)0x0004) /* Noise Error Flag */
  5647. #define USART_STATR_ORE ((uint16_t)0x0008) /* OverRun Error */
  5648. #define USART_STATR_IDLE ((uint16_t)0x0010) /* IDLE line detected */
  5649. #define USART_STATR_RXNE ((uint16_t)0x0020) /* Read Data Register Not Empty */
  5650. #define USART_STATR_TC ((uint16_t)0x0040) /* Transmission Complete */
  5651. #define USART_STATR_TXE ((uint16_t)0x0080) /* Transmit Data Register Empty */
  5652. #define USART_STATR_LBD ((uint16_t)0x0100) /* LIN Break Detection Flag */
  5653. #define USART_STATR_CTS ((uint16_t)0x0200) /* CTS Flag */
  5654. #define USART_STATR_RX_BUSY ((uint16_t)0x0400)
  5655. #define USART_STATR_MS_ERR ((uint16_t)0x0800)
  5656. /******************* Bit definition for USART_DATAR register *******************/
  5657. #define USART_DATAR_DR ((uint16_t)0x01FF) /* Data value */
  5658. /****************** Bit definition for USART_BRR register *******************/
  5659. #define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /* Fraction of USARTDIV */
  5660. #define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /* Mantissa of USARTDIV */
  5661. /****************** Bit definition for USART_CTLR1 register *******************/
  5662. #define USART_CTLR1_SBK ((uint16_t)0x0001) /* Send Break */
  5663. #define USART_CTLR1_RWU ((uint16_t)0x0002) /* Receiver wakeup */
  5664. #define USART_CTLR1_RE ((uint16_t)0x0004) /* Receiver Enable */
  5665. #define USART_CTLR1_TE ((uint16_t)0x0008) /* Transmitter Enable */
  5666. #define USART_CTLR1_IDLEIE ((uint16_t)0x0010) /* IDLE Interrupt Enable */
  5667. #define USART_CTLR1_RXNEIE ((uint16_t)0x0020) /* RXNE Interrupt Enable */
  5668. #define USART_CTLR1_TCIE ((uint16_t)0x0040) /* Transmission Complete Interrupt Enable */
  5669. #define USART_CTLR1_TXEIE ((uint16_t)0x0080) /* PE Interrupt Enable */
  5670. #define USART_CTLR1_PEIE ((uint16_t)0x0100) /* PE Interrupt Enable */
  5671. #define USART_CTLR1_PS ((uint16_t)0x0200) /* Parity Selection */
  5672. #define USART_CTLR1_PCE ((uint16_t)0x0400) /* Parity Control Enable */
  5673. #define USART_CTLR1_WAKE ((uint16_t)0x0800) /* Wakeup method */
  5674. #define USART_CTLR1_M ((uint16_t)0x1000) /* Word length */
  5675. #define USART_CTLR1_UE ((uint16_t)0x2000) /* USART Enable */
  5676. #define USART_CTLR1_M_EXT_0 ((uint16_t)0x4000)
  5677. #define USART_CTLR1_M_EXT_1 ((uint16_t)0x8000)
  5678. #define USART_CTLR1_M_EXT5 ((uint16_t)0xC000)
  5679. #define USART_CTLR1_M_EXT6 ((uint16_t)0x8000)
  5680. #define USART_CTLR1_M_EXT7 ((uint16_t)0x4000)
  5681. /****************** Bit definition for USART_CTLR2 register *******************/
  5682. #define USART_CTLR2_ADD ((uint16_t)0x000F) /* Address of the USART node */
  5683. #define USART_CTLR2_LBDL ((uint16_t)0x0020) /* LIN Break Detection Length */
  5684. #define USART_CTLR2_LBDIE ((uint16_t)0x0040) /* LIN Break Detection Interrupt Enable */
  5685. #define USART_CTLR2_LBCL ((uint16_t)0x0100) /* Last Bit Clock pulse */
  5686. #define USART_CTLR2_CPHA ((uint16_t)0x0200) /* Clock Phase */
  5687. #define USART_CTLR2_CPOL ((uint16_t)0x0400) /* Clock Polarity */
  5688. #define USART_CTLR2_CLKEN ((uint16_t)0x0800) /* Clock Enable */
  5689. #define USART_CTLR2_STOP ((uint16_t)0x3000) /* STOP[1:0] bits (STOP bits) */
  5690. #define USART_CTLR2_STOP_0 ((uint16_t)0x1000) /* Bit 0 */
  5691. #define USART_CTLR2_STOP_1 ((uint16_t)0x2000) /* Bit 1 */
  5692. #define USART_CTLR2_LINEN ((uint16_t)0x4000) /* LIN mode enable */
  5693. /****************** Bit definition for USART_CTLR3 register *******************/
  5694. #define USART_CTLR3_EIE ((uint16_t)0x0001) /* Error Interrupt Enable */
  5695. #define USART_CTLR3_IREN ((uint16_t)0x0002) /* IrDA mode Enable */
  5696. #define USART_CTLR3_IRLP ((uint16_t)0x0004) /* IrDA Low-Power */
  5697. #define USART_CTLR3_HDSEL ((uint16_t)0x0008) /* Half-Duplex Selection */
  5698. #define USART_CTLR3_NACK ((uint16_t)0x0010) /* Smartcard NACK enable */
  5699. #define USART_CTLR3_SCEN ((uint16_t)0x0020) /* Smartcard mode enable */
  5700. #define USART_CTLR3_DMAR ((uint16_t)0x0040) /* DMA Enable Receiver */
  5701. #define USART_CTLR3_DMAT ((uint16_t)0x0080) /* DMA Enable Transmitter */
  5702. #define USART_CTLR3_RTSE ((uint16_t)0x0100) /* RTS Enable */
  5703. #define USART_CTLR3_CTSE ((uint16_t)0x0200) /* CTS Enable */
  5704. #define USART_CTLR3_CTSIE ((uint16_t)0x0400) /* CTS Interrupt Enable */
  5705. #define USART_CTLR3_ONEBIT ((uint16_t)0x0800) /* One Bit method */
  5706. /****************** Bit definition for USART_GPR register ******************/
  5707. #define USART_GPR_PSC ((uint16_t)0x00FF) /* PSC[7:0] bits (Prescaler value) */
  5708. #define USART_GPR_PSC_0 ((uint16_t)0x0001) /* Bit 0 */
  5709. #define USART_GPR_PSC_1 ((uint16_t)0x0002) /* Bit 1 */
  5710. #define USART_GPR_PSC_2 ((uint16_t)0x0004) /* Bit 2 */
  5711. #define USART_GPR_PSC_3 ((uint16_t)0x0008) /* Bit 3 */
  5712. #define USART_GPR_PSC_4 ((uint16_t)0x0010) /* Bit 4 */
  5713. #define USART_GPR_PSC_5 ((uint16_t)0x0020) /* Bit 5 */
  5714. #define USART_GPR_PSC_6 ((uint16_t)0x0040) /* Bit 6 */
  5715. #define USART_GPR_PSC_7 ((uint16_t)0x0080) /* Bit 7 */
  5716. #define USART_GPR_GT ((uint16_t)0xFF00) /* Guard time value */
  5717. /****************** Bit definition for USART_CTLR4 register ******************/
  5718. #define USART_CTLR4_MS_ERRIE ((uint16_t)0x0002)
  5719. #define USART_CTLR4_CHECK_SEL ((uint16_t)0x000C)
  5720. #define USART_CTLR4_CHECK_MARKENABLE ((uint16_t)0x0008)
  5721. #define USART_CTLR4_CHECK_APACEENABLE ((uint16_t)0x000C)
  5722. /******************************************************************************/
  5723. /* OPA */
  5724. /******************************************************************************/
  5725. /******************* Bit definition for WWDG_CTLR register ********************/
  5726. #define OPA_EN1 ((uint32_t)0x0001)
  5727. #define OPA_MODE1 ((uint32_t)0x0002)
  5728. #define OPA_NSEL1 ((uint32_t)0x0004)
  5729. #define OPA_PSEL1 ((uint32_t)0x0008)
  5730. #define OPA_EN2 ((uint32_t)0x0010)
  5731. #define OPA_MODE2 ((uint32_t)0x0020)
  5732. #define OPA_NSEL2 ((uint32_t)0x0040)
  5733. #define OPA_PSEL2 ((uint32_t)0x0080)
  5734. #define OPA_EN3 ((uint32_t)0x0100)
  5735. #define OPA_MODE3 ((uint32_t)0x0200)
  5736. #define OPA_NSEL3 ((uint32_t)0x0400)
  5737. #define OPA_PSEL3 ((uint32_t)0x0800)
  5738. #define OPA_EN4 ((uint32_t)0x1000)
  5739. #define OPA_MODE4 ((uint32_t)0x2000)
  5740. #define OPA_NSEL4 ((uint32_t)0x4000)
  5741. #define OPA_PSEL4 ((uint32_t)0x8000)
  5742. /******************************************************************************/
  5743. /* Window WATCHDOG */
  5744. /******************************************************************************/
  5745. /******************* Bit definition for WWDG_CTLR register ********************/
  5746. #define WWDG_CTLR_T ((uint8_t)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */
  5747. #define WWDG_CTLR_T0 ((uint8_t)0x01) /* Bit 0 */
  5748. #define WWDG_CTLR_T1 ((uint8_t)0x02) /* Bit 1 */
  5749. #define WWDG_CTLR_T2 ((uint8_t)0x04) /* Bit 2 */
  5750. #define WWDG_CTLR_T3 ((uint8_t)0x08) /* Bit 3 */
  5751. #define WWDG_CTLR_T4 ((uint8_t)0x10) /* Bit 4 */
  5752. #define WWDG_CTLR_T5 ((uint8_t)0x20) /* Bit 5 */
  5753. #define WWDG_CTLR_T6 ((uint8_t)0x40) /* Bit 6 */
  5754. #define WWDG_CTLR_WDGA ((uint8_t)0x80) /* Activation bit */
  5755. /******************* Bit definition for WWDG_CFGR register *******************/
  5756. #define WWDG_CFGR_W ((uint16_t)0x007F) /* W[6:0] bits (7-bit window value) */
  5757. #define WWDG_CFGR_W0 ((uint16_t)0x0001) /* Bit 0 */
  5758. #define WWDG_CFGR_W1 ((uint16_t)0x0002) /* Bit 1 */
  5759. #define WWDG_CFGR_W2 ((uint16_t)0x0004) /* Bit 2 */
  5760. #define WWDG_CFGR_W3 ((uint16_t)0x0008) /* Bit 3 */
  5761. #define WWDG_CFGR_W4 ((uint16_t)0x0010) /* Bit 4 */
  5762. #define WWDG_CFGR_W5 ((uint16_t)0x0020) /* Bit 5 */
  5763. #define WWDG_CFGR_W6 ((uint16_t)0x0040) /* Bit 6 */
  5764. #define WWDG_CFGR_WDGTB ((uint16_t)0x0180) /* WDGTB[1:0] bits (Timer Base) */
  5765. #define WWDG_CFGR_WDGTB0 ((uint16_t)0x0080) /* Bit 0 */
  5766. #define WWDG_CFGR_WDGTB1 ((uint16_t)0x0100) /* Bit 1 */
  5767. #define WWDG_CFGR_EWI ((uint16_t)0x0200) /* Early Wakeup Interrupt */
  5768. /******************* Bit definition for WWDG_STATR register ********************/
  5769. #define WWDG_STATR_EWIF ((uint8_t)0x01) /* Early Wakeup Interrupt Flag */
  5770. /******************************************************************************/
  5771. /* ENHANCED FUNNCTION */
  5772. /******************************************************************************/
  5773. /**************************** Enhanced CTLR1 register *****************************/
  5774. #define EXTEN_USBD_LS ((uint32_t)0x00000001) /* Bit 0 */
  5775. #define EXTEN_USBD_PU_EN ((uint32_t)0x00000002) /* Bit 1 */
  5776. #define EXTEN_ETH_10M_EN ((uint32_t)0x00000004) /* Bit 2 */
  5777. #define EXTEN_ETH_RGMII_SEL ((uint32_t)0x00000008) /* Bit 3 */
  5778. #define EXTEN_PLL_HSI_PRE ((uint32_t)0x00000010) /* Bit 4 */
  5779. #define EXTEN_LOCKUP_EN ((uint32_t)0x00000040) /* Bit 5 */
  5780. #define EXTEN_LOCKUP_RSTF ((uint32_t)0x00000080) /* Bit 7 */
  5781. #define EXTEN_ULLDO_TRIM ((uint32_t)0x00000300) /* ULLDO_TRIM[1:0] bits */
  5782. #define EXTEN_ULLDO_TRIM0 ((uint32_t)0x00000100) /* Bit 0 */
  5783. #define EXTEN_ULLDO_TRIM1 ((uint32_t)0x00000200) /* Bit 1 */
  5784. #define EXTEN_LDO_TRIM ((uint32_t)0x00000C00) /* LDO_TRIM[1:0] bits */
  5785. #define EXTEN_LDO_TRIM0 ((uint32_t)0x00000400) /* Bit 0 */
  5786. #define EXTEN_LDO_TRIM1 ((uint32_t)0x00000800) /* Bit 1 */
  5787. #define EXTEN_HSEKPLP ((uint32_t)0x00001000)
  5788. /**************************** Enhanced CTLR2 register *****************************/
  5789. #define EXTEN_CTLR2_OPA1_HSMD ((uint32_t)0x00000001)
  5790. #define EXTEN_CTLR2_OPA2_HSMD ((uint32_t)0x00000002)
  5791. #define EXTEN_CTLR2_OPA3_HSMD ((uint32_t)0x00000004)
  5792. #define EXTEN_CTLR2_OPA4_HSMD ((uint32_t)0x00000008)
  5793. /**************************** Enhanced FEATURE_SIGN register *****************************/
  5794. #define FEATURE_SIGN_VLEVEL ((uint32_t)0x00000001)
  5795. /******************************************************************************/
  5796. /* DVP */
  5797. /******************************************************************************/
  5798. /******************* Bit definition for DVP_CR0 register ********************/
  5799. #define RB_DVP_ENABLE 0x01 // RW, DVP enable
  5800. #define RB_DVP_V_POLAR 0x02 // RW, DVP VSYNC polarity control: 1 = invert, 0 = not invert
  5801. #define RB_DVP_H_POLAR 0x04 // RW, DVP HSYNC polarity control: 1 = invert, 0 = not invert
  5802. #define RB_DVP_P_POLAR 0x08 // RW, DVP PCLK polarity control: 1 = invert, 0 = not invert
  5803. #define RB_DVP_MSK_DAT_MOD 0x30
  5804. #define RB_DVP_D8_MOD 0x00 // RW, DVP 8bits data mode
  5805. #define RB_DVP_D10_MOD 0x10 // RW, DVP 10bits data mode
  5806. #define RB_DVP_D12_MOD 0x20 // RW, DVP 12bits data mode
  5807. #define RB_DVP_JPEG 0x40 // RW, DVP JPEG mode
  5808. /******************* Bit definition for DVP_CR1 register ********************/
  5809. #define RB_DVP_DMA_EN 0x01 // RW, DVP dma enable
  5810. #define RB_DVP_ALL_CLR 0x02 // RW, DVP all clear, high action
  5811. #define RB_DVP_RCV_CLR 0x04 // RW, DVP receive logic clear, high action
  5812. #define RB_DVP_BUF_TOG 0x08 // RW, DVP bug toggle by software, write 1 to toggle, ignored writing 0
  5813. #define RB_DVP_CM 0x10 // RW, DVP capture mode
  5814. #define RB_DVP_CROP 0x20 // RW, DVP Crop feature enable
  5815. #define RB_DVP_FCRC 0xC0 // RW, DVP frame capture rate control:
  5816. #define DVP_RATE_100P 0x00 //00 = every frame captured (100%)
  5817. #define DVP_RATE_50P 0x40 //01 = every alternate frame captured (50%)
  5818. #define DVP_RATE_25P 0x80 //10 = one frame in four frame captured (25%)
  5819. /******************* Bit definition for DVP_IER register ********************/
  5820. #define RB_DVP_IE_STR_FRM 0x01 // RW, DVP frame start interrupt enable
  5821. #define RB_DVP_IE_ROW_DONE 0x02 // RW, DVP row received done interrupt enable
  5822. #define RB_DVP_IE_FRM_DONE 0x04 // RW, DVP frame received done interrupt enable
  5823. #define RB_DVP_IE_FIFO_OV 0x08 // RW, DVP receive fifo overflow interrupt enable
  5824. #define RB_DVP_IE_STP_FRM 0x10 // RW, DVP frame stop interrupt enable
  5825. /******************* Bit definition for DVP_IFR register ********************/
  5826. #define RB_DVP_IF_STR_FRM 0x01 // RW1, interrupt flag for DVP frame start
  5827. #define RB_DVP_IF_ROW_DONE 0x02 // RW1, interrupt flag for DVP row receive done
  5828. #define RB_DVP_IF_FRM_DONE 0x04 // RW1, interrupt flag for DVP frame receive done
  5829. #define RB_DVP_IF_FIFO_OV 0x08 // RW1, interrupt flag for DVP receive fifo overflow
  5830. #define RB_DVP_IF_STP_FRM 0x10 // RW1, interrupt flag for DVP frame stop
  5831. /******************* Bit definition for DVP_STATUS register ********************/
  5832. #define RB_DVP_FIFO_RDY 0x01 // RO, DVP receive fifo ready
  5833. #define RB_DVP_FIFO_FULL 0x02 // RO, DVP receive fifo full
  5834. #define RB_DVP_FIFO_OV 0x04 // RO, DVP receive fifo overflow
  5835. #define RB_DVP_MSK_FIFO_CNT 0x70 // RO, DVP receive fifo count
  5836. /******************* Bit definition for DVP_ROW_CNT register ********************/
  5837. #define RB_DVP_ROW_CNT ((uint16_t)0xFF
  5838. /******************* Bit definition for DVP_HOFFCNT register ********************/
  5839. #define RB_DVP_HOFFCNT ((uint16_t)0xFF
  5840. /******************* Bit definition for DVP_VST register ********************/
  5841. #define RB_DVP_VST ((uint16_t)0xFF
  5842. /******************* Bit definition for DVP_CAPCNT register ********************/
  5843. #define RB_DVP_CAPCNT ((uint16_t)0xFF
  5844. /******************* Bit definition for DVP_VLINE register ********************/
  5845. #define RB_DVP_VLINE ((uint16_t)0xFF
  5846. /******************* Bit definition for DVP_DR register ********************/
  5847. #define RB_DVP_DR ((uint16_t)0xFF
  5848. /******************************************************************************/
  5849. /* TKEY */
  5850. /******************************************************************************/
  5851. /******************* Bit definition for TKEY_CHARGE1 register *******************/
  5852. #define TKEY_CHARGE1_TKCG10 ((uint32_t)0x0007)
  5853. #define TKEY_CHARGE1_TKCG10_1C5 ((uint32_t)0x0000)
  5854. #define TKEY_CHARGE1_TKCG10_7C5 ((uint32_t)0x0001)
  5855. #define TKEY_CHARGE1_TKCG10_13C5 ((uint32_t)0x0002)
  5856. #define TKEY_CHARGE1_TKCG10_28C5 ((uint32_t)0x0003)
  5857. #define TKEY_CHARGE1_TKCG10_41C5 ((uint32_t)0x0004)
  5858. #define TKEY_CHARGE1_TKCG10_55C5 ((uint32_t)0x0005)
  5859. #define TKEY_CHARGE1_TKCG10_71C5 ((uint32_t)0x0006)
  5860. #define TKEY_CHARGE1_TKCG10_239C5 ((uint32_t)0x0007)
  5861. #define TKEY_CHARGE1_TKCG11 ((uint32_t)0x0038)
  5862. #define TKEY_CHARGE1_TKCG11_1C5 ((uint32_t)0x0000)
  5863. #define TKEY_CHARGE1_TKCG11_7C5 ((uint32_t)0x0008)
  5864. #define TKEY_CHARGE1_TKCG11_13C5 ((uint32_t)0x0010)
  5865. #define TKEY_CHARGE1_TKCG11_28C5 ((uint32_t)0x0018)
  5866. #define TKEY_CHARGE1_TKCG11_41C5 ((uint32_t)0x0020)
  5867. #define TKEY_CHARGE1_TKCG11_55C5 ((uint32_t)0x0028)
  5868. #define TKEY_CHARGE1_TKCG11_71C5 ((uint32_t)0x0030)
  5869. #define TKEY_CHARGE1_TKCG11_239C5 ((uint32_t)0x0038)
  5870. #define TKEY_CHARGE1_TKCG12 ((uint32_t)0x01C0)
  5871. #define TKEY_CHARGE1_TKCG12_1C5 ((uint32_t)0x0000)
  5872. #define TKEY_CHARGE1_TKCG12_7C5 ((uint32_t)0x0040)
  5873. #define TKEY_CHARGE1_TKCG12_13C5 ((uint32_t)0x0080)
  5874. #define TKEY_CHARGE1_TKCG12_28C5 ((uint32_t)0x00C0)
  5875. #define TKEY_CHARGE1_TKCG12_41C5 ((uint32_t)0x0100)
  5876. #define TKEY_CHARGE1_TKCG12_55C5 ((uint32_t)0x0140)
  5877. #define TKEY_CHARGE1_TKCG12_71C5 ((uint32_t)0x0180)
  5878. #define TKEY_CHARGE1_TKCG12_239C5 ((uint32_t)0x01C0)
  5879. #define TKEY_CHARGE1_TKCG13 ((uint32_t)0x0E00)
  5880. #define TKEY_CHARGE1_TKCG13_1C5 ((uint32_t)0x0000)
  5881. #define TKEY_CHARGE1_TKCG13_7C5 ((uint32_t)0x0200)
  5882. #define TKEY_CHARGE1_TKCG13_13C5 ((uint32_t)0x0400)
  5883. #define TKEY_CHARGE1_TKCG13_28C5 ((uint32_t)0x0600)
  5884. #define TKEY_CHARGE1_TKCG13_41C5 ((uint32_t)0x0800)
  5885. #define TKEY_CHARGE1_TKCG13_55C5 ((uint32_t)0x0A00)
  5886. #define TKEY_CHARGE1_TKCG13_71C5 ((uint32_t)0x0C00)
  5887. #define TKEY_CHARGE1_TKCG13_239C5 ((uint32_t)0x0E00)
  5888. #define TKEY_CHARGE1_TKCG14 ((uint32_t)0x7000)
  5889. #define TKEY_CHARGE1_TKCG15 ((uint32_t)0x38000)
  5890. #define TKEY_CHARGE1_TKCG16 ((uint32_t)0x1C0000)
  5891. #define TKEY_CHARGE1_TKCG17 ((uint32_t)0xE00000)
  5892. #include "ch32v30x_conf.h"
  5893. #ifdef __cplusplus
  5894. }
  5895. #endif
  5896. #endif