ch32v30x_rcc.h 20 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464
  1. /********************************** (C) COPYRIGHT *******************************
  2. * File Name : ch32v30x_rcc.h
  3. * Author : WCH
  4. * Version : V1.0.0
  5. * Date : 2024/03/06
  6. * Description : This file provides all the RCC firmware functions.
  7. *********************************************************************************
  8. * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
  9. * Attention: This software (modified or not) and binary are used for
  10. * microcontroller manufactured by Nanjing Qinheng Microelectronics.
  11. *******************************************************************************/
  12. #ifndef __CH32V30x_RCC_H
  13. #define __CH32V30x_RCC_H
  14. #ifdef __cplusplus
  15. extern "C" {
  16. #endif
  17. #include "ch32v30x.h"
  18. /* RCC_Exported_Types */
  19. typedef struct
  20. {
  21. uint32_t SYSCLK_Frequency; /* returns SYSCLK clock frequency expressed in Hz */
  22. uint32_t HCLK_Frequency; /* returns HCLK clock frequency expressed in Hz */
  23. uint32_t PCLK1_Frequency; /* returns PCLK1 clock frequency expressed in Hz */
  24. uint32_t PCLK2_Frequency; /* returns PCLK2 clock frequency expressed in Hz */
  25. uint32_t ADCCLK_Frequency; /* returns ADCCLK clock frequency expressed in Hz */
  26. }RCC_ClocksTypeDef;
  27. /* HSE_configuration */
  28. #define RCC_HSE_OFF ((uint32_t)0x00000000)
  29. #define RCC_HSE_ON ((uint32_t)0x00010000)
  30. #define RCC_HSE_Bypass ((uint32_t)0x00040000)
  31. /* PLL_entry_clock_source */
  32. #define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000)
  33. #ifdef CH32V30x_D8
  34. #define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000)
  35. #define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000)
  36. #else
  37. #define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000)
  38. #endif
  39. /* PLL_multiplication_factor */
  40. #ifdef CH32V30x_D8
  41. #define RCC_PLLMul_2 ((uint32_t)0x00000000)
  42. #define RCC_PLLMul_3 ((uint32_t)0x00040000)
  43. #define RCC_PLLMul_4 ((uint32_t)0x00080000)
  44. #define RCC_PLLMul_5 ((uint32_t)0x000C0000)
  45. #define RCC_PLLMul_6 ((uint32_t)0x00100000)
  46. #define RCC_PLLMul_7 ((uint32_t)0x00140000)
  47. #define RCC_PLLMul_8 ((uint32_t)0x00180000)
  48. #define RCC_PLLMul_9 ((uint32_t)0x001C0000)
  49. #define RCC_PLLMul_10 ((uint32_t)0x00200000)
  50. #define RCC_PLLMul_11 ((uint32_t)0x00240000)
  51. #define RCC_PLLMul_12 ((uint32_t)0x00280000)
  52. #define RCC_PLLMul_13 ((uint32_t)0x002C0000)
  53. #define RCC_PLLMul_14 ((uint32_t)0x00300000)
  54. #define RCC_PLLMul_15 ((uint32_t)0x00340000)
  55. #define RCC_PLLMul_16 ((uint32_t)0x00380000)
  56. #define RCC_PLLMul_18 ((uint32_t)0x003C0000)
  57. #else
  58. #define RCC_PLLMul_18_EXTEN ((uint32_t)0x00000000)
  59. #define RCC_PLLMul_3_EXTEN ((uint32_t)0x00040000)
  60. #define RCC_PLLMul_4_EXTEN ((uint32_t)0x00080000)
  61. #define RCC_PLLMul_5_EXTEN ((uint32_t)0x000C0000)
  62. #define RCC_PLLMul_6_EXTEN ((uint32_t)0x00100000)
  63. #define RCC_PLLMul_7_EXTEN ((uint32_t)0x00140000)
  64. #define RCC_PLLMul_8_EXTEN ((uint32_t)0x00180000)
  65. #define RCC_PLLMul_9_EXTEN ((uint32_t)0x001C0000)
  66. #define RCC_PLLMul_10_EXTEN ((uint32_t)0x00200000)
  67. #define RCC_PLLMul_11_EXTEN ((uint32_t)0x00240000)
  68. #define RCC_PLLMul_12_EXTEN ((uint32_t)0x00280000)
  69. #define RCC_PLLMul_13_EXTEN ((uint32_t)0x002C0000)
  70. #define RCC_PLLMul_14_EXTEN ((uint32_t)0x00300000)
  71. #define RCC_PLLMul_6_5_EXTEN ((uint32_t)0x00340000)
  72. #define RCC_PLLMul_15_EXTEN ((uint32_t)0x00380000)
  73. #define RCC_PLLMul_16_EXTEN ((uint32_t)0x003C0000)
  74. #endif
  75. /* PREDIV1_division_factor */
  76. #ifdef CH32V30x_D8C
  77. #define RCC_PREDIV1_Div1 ((uint32_t)0x00000000)
  78. #define RCC_PREDIV1_Div2 ((uint32_t)0x00000001)
  79. #define RCC_PREDIV1_Div3 ((uint32_t)0x00000002)
  80. #define RCC_PREDIV1_Div4 ((uint32_t)0x00000003)
  81. #define RCC_PREDIV1_Div5 ((uint32_t)0x00000004)
  82. #define RCC_PREDIV1_Div6 ((uint32_t)0x00000005)
  83. #define RCC_PREDIV1_Div7 ((uint32_t)0x00000006)
  84. #define RCC_PREDIV1_Div8 ((uint32_t)0x00000007)
  85. #define RCC_PREDIV1_Div9 ((uint32_t)0x00000008)
  86. #define RCC_PREDIV1_Div10 ((uint32_t)0x00000009)
  87. #define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A)
  88. #define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B)
  89. #define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C)
  90. #define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D)
  91. #define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E)
  92. #define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F)
  93. #endif
  94. /* PREDIV1_clock_source */
  95. #ifdef CH32V30x_D8C
  96. #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000)
  97. #define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000)
  98. #endif
  99. /* PREDIV2_division_factor */
  100. #ifdef CH32V30x_D8C
  101. #define RCC_PREDIV2_Div1 ((uint32_t)0x00000000)
  102. #define RCC_PREDIV2_Div2 ((uint32_t)0x00000010)
  103. #define RCC_PREDIV2_Div3 ((uint32_t)0x00000020)
  104. #define RCC_PREDIV2_Div4 ((uint32_t)0x00000030)
  105. #define RCC_PREDIV2_Div5 ((uint32_t)0x00000040)
  106. #define RCC_PREDIV2_Div6 ((uint32_t)0x00000050)
  107. #define RCC_PREDIV2_Div7 ((uint32_t)0x00000060)
  108. #define RCC_PREDIV2_Div8 ((uint32_t)0x00000070)
  109. #define RCC_PREDIV2_Div9 ((uint32_t)0x00000080)
  110. #define RCC_PREDIV2_Div10 ((uint32_t)0x00000090)
  111. #define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0)
  112. #define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0)
  113. #define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0)
  114. #define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0)
  115. #define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0)
  116. #define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0)
  117. #endif
  118. /* PLL2_multiplication_factor */
  119. #ifdef CH32V30x_D8C
  120. #define RCC_PLL2Mul_2_5 ((uint32_t)0x00000000)
  121. #define RCC_PLL2Mul_12_5 ((uint32_t)0x00000100)
  122. #define RCC_PLL2Mul_4 ((uint32_t)0x00000200)
  123. #define RCC_PLL2Mul_5 ((uint32_t)0x00000300)
  124. #define RCC_PLL2Mul_6 ((uint32_t)0x00000400)
  125. #define RCC_PLL2Mul_7 ((uint32_t)0x00000500)
  126. #define RCC_PLL2Mul_8 ((uint32_t)0x00000600)
  127. #define RCC_PLL2Mul_9 ((uint32_t)0x00000700)
  128. #define RCC_PLL2Mul_10 ((uint32_t)0x00000800)
  129. #define RCC_PLL2Mul_11 ((uint32_t)0x00000900)
  130. #define RCC_PLL2Mul_12 ((uint32_t)0x00000A00)
  131. #define RCC_PLL2Mul_13 ((uint32_t)0x00000B00)
  132. #define RCC_PLL2Mul_14 ((uint32_t)0x00000C00)
  133. #define RCC_PLL2Mul_15 ((uint32_t)0x00000D00)
  134. #define RCC_PLL2Mul_16 ((uint32_t)0x00000E00)
  135. #define RCC_PLL2Mul_20 ((uint32_t)0x00000F00)
  136. #endif
  137. /* PLL3_multiplication_factor */
  138. #ifdef CH32V30x_D8C
  139. #define RCC_PLL3Mul_2_5 ((uint32_t)0x00000000)
  140. #define RCC_PLL3Mul_12_5 ((uint32_t)0x00001000)
  141. #define RCC_PLL3Mul_4 ((uint32_t)0x00002000)
  142. #define RCC_PLL3Mul_5 ((uint32_t)0x00003000)
  143. #define RCC_PLL3Mul_6 ((uint32_t)0x00004000)
  144. #define RCC_PLL3Mul_7 ((uint32_t)0x00005000)
  145. #define RCC_PLL3Mul_8 ((uint32_t)0x00006000)
  146. #define RCC_PLL3Mul_9 ((uint32_t)0x00007000)
  147. #define RCC_PLL3Mul_10 ((uint32_t)0x00008000)
  148. #define RCC_PLL3Mul_11 ((uint32_t)0x00009000)
  149. #define RCC_PLL3Mul_12 ((uint32_t)0x0000A000)
  150. #define RCC_PLL3Mul_13 ((uint32_t)0x0000B000)
  151. #define RCC_PLL3Mul_14 ((uint32_t)0x0000C000)
  152. #define RCC_PLL3Mul_15 ((uint32_t)0x0000D000)
  153. #define RCC_PLL3Mul_16 ((uint32_t)0x0000E000)
  154. #define RCC_PLL3Mul_20 ((uint32_t)0x0000F000)
  155. #endif
  156. /* System_clock_source */
  157. #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
  158. #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
  159. #define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
  160. /* AHB_clock_source */
  161. #define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
  162. #define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
  163. #define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
  164. #define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
  165. #define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
  166. #define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
  167. #define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
  168. #define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
  169. #define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
  170. /* APB1_APB2_clock_source */
  171. #define RCC_HCLK_Div1 ((uint32_t)0x00000000)
  172. #define RCC_HCLK_Div2 ((uint32_t)0x00000400)
  173. #define RCC_HCLK_Div4 ((uint32_t)0x00000500)
  174. #define RCC_HCLK_Div8 ((uint32_t)0x00000600)
  175. #define RCC_HCLK_Div16 ((uint32_t)0x00000700)
  176. /* RCC_Interrupt_source */
  177. #define RCC_IT_LSIRDY ((uint8_t)0x01)
  178. #define RCC_IT_LSERDY ((uint8_t)0x02)
  179. #define RCC_IT_HSIRDY ((uint8_t)0x04)
  180. #define RCC_IT_HSERDY ((uint8_t)0x08)
  181. #define RCC_IT_PLLRDY ((uint8_t)0x10)
  182. #define RCC_IT_CSS ((uint8_t)0x80)
  183. #ifdef CH32V30x_D8C
  184. #define RCC_IT_PLL2RDY ((uint8_t)0x20)
  185. #define RCC_IT_PLL3RDY ((uint8_t)0x40)
  186. #endif
  187. /* USBFS_clock_source */
  188. #define RCC_USBFSCLKSource_PLLCLK_Div1 ((uint8_t)0x00)
  189. #define RCC_USBFSCLKSource_PLLCLK_Div2 ((uint8_t)0x01)
  190. #define RCC_USBFSCLKSource_PLLCLK_Div3 ((uint8_t)0x02)
  191. #define RCC_OTGFSCLKSource_PLLCLK_Div1 RCC_USBFSCLKSource_PLLCLK_Div1
  192. #define RCC_OTGFSCLKSource_PLLCLK_Div2 RCC_USBFSCLKSource_PLLCLK_Div2
  193. #define RCC_OTGFSCLKSource_PLLCLK_Div3 RCC_USBFSCLKSource_PLLCLK_Div3
  194. /* I2S2_clock_source */
  195. #ifdef CH32V30x_D8C
  196. #define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00)
  197. #define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01)
  198. #endif
  199. /* I2S3_clock_source */
  200. #ifdef CH32V30x_D8C
  201. #define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00)
  202. #define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01)
  203. #endif
  204. /* ADC_clock_source */
  205. #define RCC_PCLK2_Div2 ((uint32_t)0x00000000)
  206. #define RCC_PCLK2_Div4 ((uint32_t)0x00004000)
  207. #define RCC_PCLK2_Div6 ((uint32_t)0x00008000)
  208. #define RCC_PCLK2_Div8 ((uint32_t)0x0000C000)
  209. /* LSE_configuration */
  210. #define RCC_LSE_OFF ((uint8_t)0x00)
  211. #define RCC_LSE_ON ((uint8_t)0x01)
  212. #define RCC_LSE_Bypass ((uint8_t)0x04)
  213. /* RTC_clock_source */
  214. #define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
  215. #define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
  216. #define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300)
  217. /* AHB_peripheral */
  218. #define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
  219. #define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002)
  220. #define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)
  221. #define RCC_AHBPeriph_CRC ((uint32_t)0x00000040)
  222. #define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100)
  223. #define RCC_AHBPeriph_RNG ((uint32_t)0x00000200)
  224. #define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400)
  225. #define RCC_AHBPeriph_USBHS ((uint32_t)0x00000800)
  226. #define RCC_AHBPeriph_USBFS ((uint32_t)0x00001000)
  227. #define RCC_AHBPeriph_DVP ((uint32_t)0x00002000)
  228. #define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000)
  229. #define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000)
  230. #define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000)
  231. #define RCC_AHBPeriph_OTG_FS RCC_AHBPeriph_USBFS
  232. /* APB2_peripheral */
  233. #define RCC_APB2Periph_AFIO ((uint32_t)0x00000001)
  234. #define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)
  235. #define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008)
  236. #define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)
  237. #define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020)
  238. #define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040)
  239. #define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)
  240. #define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400)
  241. #define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)
  242. #define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
  243. #define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000)
  244. #define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)
  245. #define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000)
  246. #define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000)
  247. /* APB1_peripheral */
  248. #define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
  249. #define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
  250. #define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
  251. #define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
  252. #define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
  253. #define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
  254. #define RCC_APB1Periph_UART6 ((uint32_t)0x00000040)
  255. #define RCC_APB1Periph_UART7 ((uint32_t)0x00000080)
  256. #define RCC_APB1Periph_UART8 ((uint32_t)0x00000100)
  257. #define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
  258. #define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
  259. #define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
  260. #define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
  261. #define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
  262. #define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
  263. #define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
  264. #define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
  265. #define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
  266. #define RCC_APB1Periph_USB ((uint32_t)0x00800000)
  267. #define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
  268. #define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
  269. #define RCC_APB1Periph_BKP ((uint32_t)0x08000000)
  270. #define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
  271. #define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
  272. /* Clock_source_to_output_on_MCO_pin */
  273. #define RCC_MCO_NoClock ((uint8_t)0x00)
  274. #define RCC_MCO_SYSCLK ((uint8_t)0x04)
  275. #define RCC_MCO_HSI ((uint8_t)0x05)
  276. #define RCC_MCO_HSE ((uint8_t)0x06)
  277. #define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07)
  278. #ifdef CH32V30x_D8C
  279. #define RCC_MCO_PLL2CLK ((uint8_t)0x08)
  280. #define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09)
  281. #define RCC_MCO_XT1 ((uint8_t)0x0A)
  282. #define RCC_MCO_PLL3CLK ((uint8_t)0x0B)
  283. #endif
  284. /* RCC_Flag */
  285. #define RCC_FLAG_HSIRDY ((uint8_t)0x21)
  286. #define RCC_FLAG_HSERDY ((uint8_t)0x31)
  287. #define RCC_FLAG_PLLRDY ((uint8_t)0x39)
  288. #define RCC_FLAG_LSERDY ((uint8_t)0x41)
  289. #define RCC_FLAG_LSIRDY ((uint8_t)0x61)
  290. #define RCC_FLAG_PINRST ((uint8_t)0x7A)
  291. #define RCC_FLAG_PORRST ((uint8_t)0x7B)
  292. #define RCC_FLAG_SFTRST ((uint8_t)0x7C)
  293. #define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
  294. #define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
  295. #define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
  296. #ifdef CH32V30x_D8C
  297. #define RCC_FLAG_PLL2RDY ((uint8_t)0x3B)
  298. #define RCC_FLAG_PLL3RDY ((uint8_t)0x3D)
  299. #endif
  300. /* SysTick_clock_source */
  301. #define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
  302. #define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
  303. /* RNG_clock_source */
  304. #ifdef CH32V30x_D8C
  305. #define RCC_RNGCLKSource_SYSCLK ((uint32_t)0x00)
  306. #define RCC_RNGCLKSource_PLL3_VCO ((uint32_t)0x01)
  307. #endif
  308. /* ETH1G_clock_source */
  309. #ifdef CH32V30x_D8C
  310. #define RCC_ETH1GCLKSource_PLL2_VCO ((uint32_t)0x00)
  311. #define RCC_ETH1GCLKSource_PLL3_VCO ((uint32_t)0x01)
  312. #define RCC_ETH1GCLKSource_PB1_IN ((uint32_t)0x02)
  313. #endif
  314. /* USBFS_clock_source */
  315. #ifdef CH32V30x_D8C
  316. #define RCC_USBPLL_Div1 ((uint32_t)0x00)
  317. #define RCC_USBPLL_Div2 ((uint32_t)0x01)
  318. #define RCC_USBPLL_Div3 ((uint32_t)0x02)
  319. #define RCC_USBPLL_Div4 ((uint32_t)0x03)
  320. #define RCC_USBPLL_Div5 ((uint32_t)0x04)
  321. #define RCC_USBPLL_Div6 ((uint32_t)0x05)
  322. #define RCC_USBPLL_Div7 ((uint32_t)0x06)
  323. #define RCC_USBPLL_Div8 ((uint32_t)0x07)
  324. #endif
  325. /* USBHSPLL_clock_source */
  326. #ifdef CH32V30x_D8C
  327. #define RCC_HSBHSPLLCLKSource_HSE ((uint32_t)0x00)
  328. #define RCC_HSBHSPLLCLKSource_HSI ((uint32_t)0x01)
  329. #endif
  330. /* USBHSPLLCKREF_clock_select */
  331. #ifdef CH32V30x_D8C
  332. #define RCC_USBHSPLLCKREFCLK_3M ((uint32_t)0x00)
  333. #define RCC_USBHSPLLCKREFCLK_4M ((uint32_t)0x01)
  334. #define RCC_USBHSPLLCKREFCLK_8M ((uint32_t)0x02)
  335. #define RCC_USBHSPLLCKREFCLK_5M ((uint32_t)0x03)
  336. #endif
  337. /* OTGUSBCLK48M_clock_source */
  338. #define RCC_USBCLK48MCLKSource_PLLCLK ((uint32_t)0x00)
  339. #define RCC_USBCLK48MCLKSource_USBPHY ((uint32_t)0x01)
  340. void RCC_DeInit(void);
  341. void RCC_HSEConfig(uint32_t RCC_HSE);
  342. ErrorStatus RCC_WaitForHSEStartUp(void);
  343. void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
  344. void RCC_HSICmd(FunctionalState NewState);
  345. void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
  346. void RCC_PLLCmd(FunctionalState NewState);
  347. void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
  348. uint8_t RCC_GetSYSCLKSource(void);
  349. void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
  350. void RCC_PCLK1Config(uint32_t RCC_HCLK);
  351. void RCC_PCLK2Config(uint32_t RCC_HCLK);
  352. void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
  353. void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
  354. void RCC_LSEConfig(uint8_t RCC_LSE);
  355. void RCC_LSICmd(FunctionalState NewState);
  356. void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
  357. void RCC_RTCCLKCmd(FunctionalState NewState);
  358. void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
  359. void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
  360. void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
  361. void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
  362. void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
  363. void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
  364. void RCC_BackupResetCmd(FunctionalState NewState);
  365. void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
  366. void RCC_MCOConfig(uint8_t RCC_MCO);
  367. FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
  368. void RCC_ClearFlag(void);
  369. ITStatus RCC_GetITStatus(uint8_t RCC_IT);
  370. void RCC_ClearITPendingBit(uint8_t RCC_IT);
  371. void RCC_ADCCLKADJcmd(FunctionalState NewState);
  372. void RCC_USBFSCLKConfig(uint32_t RCC_USBFSCLKSource);
  373. void RCC_USBCLK48MConfig(uint32_t RCC_USBCLK48MSource);
  374. #define RCC_OTGFSCLKConfig RCC_USBFSCLKConfig
  375. #ifdef CH32V30x_D8C
  376. void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div);
  377. void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div);
  378. void RCC_PLL2Config(uint32_t RCC_PLL2Mul);
  379. void RCC_PLL2Cmd(FunctionalState NewState);
  380. void RCC_PLL3Config(uint32_t RCC_PLL3Mul);
  381. void RCC_PLL3Cmd(FunctionalState NewState);
  382. void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource);
  383. void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource);
  384. void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
  385. void RCC_RNGCLKConfig(uint32_t RCC_RNGCLKSource);
  386. void RCC_ETH1GCLKConfig(uint32_t RCC_ETH1GCLKSource);
  387. void RCC_ETH1G_125Mcmd(FunctionalState NewState);
  388. void RCC_USBHSConfig(uint32_t RCC_USBHS);
  389. void RCC_USBHSPLLCLKConfig(uint32_t RCC_USBHSPLLCLKSource);
  390. void RCC_USBHSPLLCKREFCLKConfig(uint32_t RCC_USBHSPLLCKREFCLKSource);
  391. void RCC_USBHSPHYPLLALIVEcmd(FunctionalState NewState);
  392. #endif
  393. #ifdef __cplusplus
  394. }
  395. #endif
  396. #endif