ch32v30x_pwr.c 9.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361
  1. /********************************** (C) COPYRIGHT *******************************
  2. * File Name : ch32v30x_pwr.c
  3. * Author : WCH
  4. * Version : V1.0.0
  5. * Date : 2021/06/06
  6. * Description : This file provides all the PWR firmware functions.
  7. *********************************************************************************
  8. * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
  9. * Attention: This software (modified or not) and binary are used for
  10. * microcontroller manufactured by Nanjing Qinheng Microelectronics.
  11. *******************************************************************************/
  12. #include "ch32v30x_pwr.h"
  13. #include "ch32v30x_rcc.h"
  14. /* PWR registers bit mask */
  15. /* CTLR register bit mask */
  16. #define CTLR_DS_MASK ((uint32_t)0xFFFFFFFC)
  17. #define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F)
  18. /*********************************************************************
  19. * @fn PWR_DeInit
  20. *
  21. * @brief Deinitializes the PWR peripheral registers to their default
  22. * reset values.
  23. *
  24. * @return none
  25. */
  26. void PWR_DeInit(void)
  27. {
  28. RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
  29. RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
  30. }
  31. /*********************************************************************
  32. * @fn PWR_BackupAccessCmd
  33. *
  34. * @brief Enables or disables access to the RTC and backup registers.
  35. *
  36. * @param NewState - new state of the access to the RTC and backup registers,
  37. * This parameter can be: ENABLE or DISABLE.
  38. *
  39. * @return none
  40. */
  41. void PWR_BackupAccessCmd(FunctionalState NewState)
  42. {
  43. if(NewState)
  44. {
  45. PWR->CTLR |= (1 << 8);
  46. }
  47. else
  48. {
  49. PWR->CTLR &= ~(1 << 8);
  50. }
  51. }
  52. /*********************************************************************
  53. * @fn PWR_PVDCmd
  54. *
  55. * @brief Enables or disables the Power Voltage Detector(PVD).
  56. *
  57. * @param NewState - new state of the PVD(ENABLE or DISABLE).
  58. *
  59. * @return none
  60. */
  61. void PWR_PVDCmd(FunctionalState NewState)
  62. {
  63. if(NewState)
  64. {
  65. PWR->CTLR |= (1 << 4);
  66. }
  67. else
  68. {
  69. PWR->CTLR &= ~(1 << 4);
  70. }
  71. }
  72. /*********************************************************************
  73. * @fn PWR_PVDLevelConfig
  74. *
  75. * @brief Configures the voltage threshold detected by the Power Voltage
  76. * Detector(PVD).
  77. *
  78. * @param PWR_PVDLevel - specifies the PVD detection level
  79. * PWR_PVDLevel_MODE0 - PVD detection level set to mode 0.
  80. * PWR_PVDLevel_MODE1 - PVD detection level set to mode 1.
  81. * PWR_PVDLevel_MODE2 - PVD detection level set to mode 2.
  82. * PWR_PVDLevel_MODE3 - PVD detection level set to mode 3.
  83. * PWR_PVDLevel_MODE4 - PVD detection level set to mode 4.
  84. * PWR_PVDLevel_MODE5 - PVD detection level set to mode 5.
  85. * PWR_PVDLevel_MODE6 - PVD detection level set to mode 6.
  86. * PWR_PVDLevel_MODE7 - PVD detection level set to mode 7.
  87. *
  88. * @return none
  89. */
  90. void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
  91. {
  92. uint32_t tmpreg = 0;
  93. tmpreg = PWR->CTLR;
  94. tmpreg &= CTLR_PLS_MASK;
  95. tmpreg |= PWR_PVDLevel;
  96. PWR->CTLR = tmpreg;
  97. }
  98. /*********************************************************************
  99. * @fn PWR_WakeUpPinCmd
  100. *
  101. * @brief Enables or disables the WakeUp Pin functionality.
  102. *
  103. * @param NewState - new state of the WakeUp Pin functionality
  104. * (ENABLE or DISABLE).
  105. *
  106. * @return none
  107. */
  108. void PWR_WakeUpPinCmd(FunctionalState NewState)
  109. {
  110. if(NewState)
  111. {
  112. PWR->CSR |= (1 << 8);
  113. }
  114. else
  115. {
  116. PWR->CSR &= ~(1 << 8);
  117. }
  118. }
  119. /*********************************************************************
  120. * @fn PWR_EnterSTOPMode
  121. *
  122. * @brief Enters STOP mode.
  123. *
  124. * @param PWR_Regulator - specifies the regulator state in STOP mode.
  125. * PWR_Regulator_ON - STOP mode with regulator ON
  126. * PWR_Regulator_LowPower - STOP mode with regulator in low power mode
  127. * PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction.
  128. * PWR_STOPEntry_WFI - enter STOP mode with WFI instruction
  129. * PWR_STOPEntry_WFE - enter STOP mode with WFE instruction
  130. *
  131. * @return none
  132. */
  133. void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
  134. {
  135. uint32_t tmpreg = 0;
  136. tmpreg = PWR->CTLR;
  137. tmpreg &= CTLR_DS_MASK;
  138. tmpreg |= PWR_Regulator;
  139. PWR->CTLR = tmpreg;
  140. NVIC->SCTLR |= (1 << 2);
  141. if(PWR_STOPEntry == PWR_STOPEntry_WFI)
  142. {
  143. __WFI();
  144. }
  145. else
  146. {
  147. __WFE();
  148. }
  149. NVIC->SCTLR &= ~(1 << 2);
  150. }
  151. /*********************************************************************
  152. * @fn PWR_EnterSTANDBYMode
  153. *
  154. * @brief Enters STANDBY mode.
  155. *
  156. * @return none
  157. */
  158. void PWR_EnterSTANDBYMode(void)
  159. {
  160. PWR->CTLR |= PWR_CTLR_CWUF;
  161. PWR->CTLR |= PWR_CTLR_PDDS;
  162. NVIC->SCTLR |= (1 << 2);
  163. __WFI();
  164. }
  165. /*********************************************************************
  166. * @fn PWR_GetFlagStatus
  167. *
  168. * @brief Checks whether the specified PWR flag is set or not.
  169. *
  170. * @param PWR_FLAG - specifies the flag to check.
  171. * PWR_FLAG_WU - Wake Up flag
  172. * PWR_FLAG_SB - StandBy flag
  173. * PWR_FLAG_PVDO - PVD Output
  174. *
  175. * @return The new state of PWR_FLAG (SET or RESET).
  176. */
  177. FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
  178. {
  179. FlagStatus bitstatus = RESET;
  180. if((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
  181. {
  182. bitstatus = SET;
  183. }
  184. else
  185. {
  186. bitstatus = RESET;
  187. }
  188. return bitstatus;
  189. }
  190. /*********************************************************************
  191. * @fn PWR_ClearFlag
  192. *
  193. * @brief Clears the PWR's pending flags.
  194. *
  195. * @param PWR_FLAG - specifies the flag to clear.
  196. * PWR_FLAG_WU - Wake Up flag
  197. * PWR_FLAG_SB - StandBy flag
  198. *
  199. * @return none
  200. */
  201. void PWR_ClearFlag(uint32_t PWR_FLAG)
  202. {
  203. PWR->CTLR |= PWR_FLAG << 2;
  204. }
  205. /*********************************************************************
  206. * @fn PWR_EnterSTANDBYMode_RAM
  207. *
  208. * @brief Enters STANDBY mode with RAM data retention function on.
  209. *
  210. * @return none
  211. */
  212. void PWR_EnterSTANDBYMode_RAM(void)
  213. {
  214. uint32_t tmpreg = 0;
  215. tmpreg = PWR->CTLR;
  216. tmpreg |= PWR_CTLR_CWUF;
  217. tmpreg |= PWR_CTLR_PDDS;
  218. //2K+30K in standby w power.
  219. tmpreg |= (0x1 << 16) | (0x1 << 17);
  220. PWR->CTLR = tmpreg;
  221. NVIC->SCTLR |= (1 << 2);
  222. __WFI();
  223. }
  224. /*********************************************************************
  225. * @fn PWR_EnterSTANDBYMode_RAM_LV
  226. *
  227. * @brief Enters STANDBY mode with RAM data retention function and LV mode on.
  228. *
  229. * @return none
  230. */
  231. void PWR_EnterSTANDBYMode_RAM_LV(void)
  232. {
  233. uint32_t tmpreg = 0;
  234. tmpreg = PWR->CTLR;
  235. tmpreg |= PWR_CTLR_CWUF;
  236. tmpreg |= PWR_CTLR_PDDS;
  237. //2K+30K in standby power.
  238. tmpreg |= (0x1 << 16) | (0x1 << 17);
  239. //2K+30K in standby LV .
  240. tmpreg |= (0x1 << 20);
  241. PWR->CTLR = tmpreg;
  242. NVIC->SCTLR |= (1 << 2);
  243. __WFI();
  244. }
  245. /*********************************************************************
  246. * @fn PWR_EnterSTANDBYMode_RAM_VBAT_EN
  247. *
  248. * @brief Enters STANDBY mode with RAM data retention function on (VBAT Enable).
  249. *
  250. * @return none
  251. */
  252. void PWR_EnterSTANDBYMode_RAM_VBAT_EN(void)
  253. {
  254. uint32_t tmpreg = 0;
  255. tmpreg = PWR->CTLR;
  256. tmpreg |= PWR_CTLR_CWUF;
  257. tmpreg |= PWR_CTLR_PDDS;
  258. //2K+30K in standby power (VBAT Enable).
  259. tmpreg |= (0x1 << 18) | (0x1 << 19);
  260. PWR->CTLR = tmpreg;
  261. NVIC->SCTLR |= (1 << 2);
  262. __WFI();
  263. }
  264. /*********************************************************************
  265. * @fn PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN
  266. *
  267. * @brief Enters STANDBY mode with RAM data retention function and LV mode on(VBAT Enable).
  268. *
  269. * @return none
  270. */
  271. void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void)
  272. {
  273. uint32_t tmpreg = 0;
  274. tmpreg = PWR->CTLR;
  275. tmpreg |= PWR_CTLR_CWUF;
  276. tmpreg |= PWR_CTLR_PDDS;
  277. //2K+30K in standby power (VBAT Enable).
  278. tmpreg |= (0x1 << 18) | (0x1 << 19);
  279. //2K+30K in standby LV .
  280. tmpreg |= (0x1 << 20);
  281. PWR->CTLR = tmpreg;
  282. NVIC->SCTLR |= (1 << 2);
  283. __WFI();
  284. }
  285. /*********************************************************************
  286. * @fn PWR_EnterSTOPMode_RAM_LV
  287. *
  288. * @brief Enters STOP mode with RAM data retention function and LV mode on.
  289. *
  290. * @param PWR_Regulator - specifies the regulator state in STOP mode.
  291. * PWR_Regulator_LowPower - STOP mode with regulator in low power mode
  292. * PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction.
  293. * PWR_STOPEntry_WFI - enter STOP mode with WFI instruction
  294. * PWR_STOPEntry_WFE - enter STOP mode with WFE instruction
  295. *
  296. * @return none
  297. */
  298. void PWR_EnterSTOPMode_RAM_LV(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
  299. {
  300. uint32_t tmpreg = 0;
  301. tmpreg = PWR->CTLR;
  302. tmpreg &= CTLR_DS_MASK;
  303. tmpreg |= PWR_Regulator;
  304. tmpreg |= (0x1 << 20);
  305. PWR->CTLR = tmpreg;
  306. NVIC->SCTLR |= (1 << 2);
  307. if(PWR_STOPEntry == PWR_STOPEntry_WFI)
  308. {
  309. __WFI();
  310. }
  311. else
  312. {
  313. __WFE();
  314. }
  315. NVIC->SCTLR &= ~(1 << 2);
  316. }